AR# 20837 12.1 Route - How do I debug a case where PAR fails to route all nets?
Description
When PAR fails to successfully route all of the signals, the root cause can be one of several things including:
1. A component may be configured in such a way that it is unroutable. An example would be a V4 design with ILOGIC and OLOGIC components in adjacent sites that have different SR signals. These components share a routing resource to the SR pin, so they must use the same SR signal. Otherwise, one of the signals will be unroutable. The root cause of this problem is a MAP packing issue.
2. A component may be placed such that it is unroutable. An example would be a carry chain that is not aligned properly by the placer so that the dedicated COUT-->CIN resource can be used. The router will attempt to use a BX-->CIN route-thru, but if the slices is already using the BX pin for something else, then the carry net is unroutable. The root cause of this problem is in the placer.
3. A design may also be unroutable due to congestion. There may simply be too many connections in the design for the router to find a solution.
4. A design may be unroutable due to over-constraining of timing. The placement and routing decisions that are a compromise between routability needs and timing needs. If the timing needs are too heaviliy weighted, then the routability can suffer.
Solution
Identify the Unroutable Net(s) Involved
The router will have done one of several things:
1. Router ran to completion with one or a few unrouted nets without any warning messages about unroutable nets. The nets involved can be identified in FPGA Editor or by examining the text file design.unroutes in the project directory.
2. Router printed warning about unroutable nets and then ran to completion with one or a few unrouted nets. The nets involved can be identified from the information in the router messages that are capture in the .par log file.
WARNING:Route:436 - The router has detected an unroutable situation for one or
more connections. The router will finish the rest of the design and leave
them as unrouted, The cause of this behavior is either an issue with the
placement or unroutable placement constraints. To allow you to use FPGA
editor to isolate the problems, the following is a list of (up to 10) such
unroutable connections:
Unroutable signal: mazama_core/packet_rst_soft_i pin:
mazama_core/mazama_packet_handler/enterasys_4bit_channel_rx_dual_wrap3/enterasys
_4bit_channel_rx0/enterasys_4bit_channel_rx_stage2/enterasys_4bit_channel_crc_sh
ell/curr_crc_st[25]/D6
3. Router printed error messages and then stopped without attempting to complete the design. The nets involved can be identified from the information in the router messages that are captured in the .par log file.
ERROR:Route:547 - Found unroutable pin <COUNT_OUT_OSERDES_P.DIFFO_OUT> placed at </IOB_X0Y25> on net
<COUNT_OUT_OBUFDS_INST/SLAVEBUF.DIFFOUT>.
ERROR:Route:471 -
This design is unroutable. Router will not continue. To evaluate the problem please use fpga_editor. The nets listed below can not be
routed:
4. The Router was unable to complete routing with many unrouted nets. This failure is usually due to placer congestion and is beyond the scope of this Answer Record.
Examine the unroutable net in FPGA Editor
Load the design in FPGA Editor (FED) and set the list window to "unrouted nets". Highlight the unrouted nets and then zoom in on them to examine the pin connectivity involved. Or if the router quit without routing and all nets are unrouted, use the find button to search for the net name mentioned in the Route:547 message. Once the net is selected you can examine the net connectivity using the net attribute window:
Select a pin and select the "Go to" button to zoom in on the pin. This allows you to navigate around the net and examine the net connectivity.
Common Issues to Look For
- Carry Chains that are not aligned and BX pin not available for route-thru
- Too many global signals driving non-clock pins in a tile
- Differential I/O Pair not placed together in paired sites
- Clock Region over populated with too many global nets. No clock spines unused.
- Directed Route blocking switchbox route path to pin.
- BUFIO or BUFR with loads not constrained within reach
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