We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20891

6.3 EDK_XPS - Base System Builder and Clock combination limitation


Keywords: GUI, frequency

Urgency: Standard

General Description:
I am using the Base System Builder to create my project in EDK. My project's reference clock is different from the setting provided in the GUI. The Base System Builder Configure Processor GUI screen is restrictive.

How can I create my own clock combination?


The Base System Builder is a wizard that is designed to help you create your system. It does not cater to every possible combination of system, so not all clock combinations are included.

If your system requires a different set of working frequencies, you can use the Dcm_modules to configure the DCM to meet your specific system requirements.
AR# 20891
Date Created 03/02/2005
Last Updated 04/12/2007
Status Archive
Type General Article