UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20895

6.3 System Generator for DSP - Why does my output appear to be saturated when doing JTAG Hardware in the Loop Co-Simulation?

Description

General Description: 

Why does my output appear to be saturated when doing JTAG Hardware in the Loop Co-Simulation?

Solution

This usually occurs when the JTAG chain is not correctly defined. 

 

You must make sure to define the register lengths for all the devices in the chain. 

 

You can find more information about JTAG Hardware in the Loop Co-Simulation under the Using FPGA Hardware in the Loop of the System Generator for DSP Users Guide. 

 

http://www.xilinx.com/products/software/sysgen/app_docs/user_guide.htm

AR# 20895
Date Created 09/03/2007
Last Updated 05/19/2014
Status Archive
Type General Article