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AR# 20897

LogiCORE PCI/PCI-X - Synplicity is removing the IDELAYCTRL from the wrapper file

Description

General Description:

Some Virtex-4 PCI and PCI-X designs make use of the IDELAYCTRL module. This is instantiated in the core wrapper file. For example, it can be found in the pcim_lc_66_3_r.v (vhd) or pcix_lc_64ng.v (vhd) files. The instanantiation looks like this:

Verilog:

IDELAYCTRL XPCI_IDC0 (.RDY(),.REFCLK(REFCLK),.RST(REFRST));

IDELAYCTRL XPCI_IDC1 (.RDY(),.REFCLK(REFCLK),.RST(REFRST));

IDELAYCTRL XPCI_IDC2 (.RDY(),.REFCLK(REFCLK),.RST(REFRST));

VHDL:

XPCI_IDC0 : IDELAYCTRL port map

( RDY => OPEN, REFCLK => REFCLK, RST => REFRST );

XPCI_IDC1 : IDELAYCTRL port map

( RDY => OPEN, REFCLK => REFCLK, RST => REFRST );

XPCI_IDC2 : IDELAYCTRL port map

( RDY => OPEN, REFCLK => REFCLK, RST => REFRST );

Because the RDY output of this module is not connected, Synplify removes or prunes the module from the design.

Solution

It is valid to use the IDELAYCTRL module without hooking up the output. To work around this, you can use the syn_noprune attribute. Please modify the wrapper file to include the following:

Verilog

IDELAYCTRL XPCI_IDC0 (.RDY(),.REFCLK(REFCLK),.RST(REFRST)) /* synthesis syn_noprune=1 */;

IDELAYCTRL XPCI_IDC1 (.RDY(),.REFCLK(REFCLK),.RST(REFRST)) /* synthesis syn_noprune=1 */;

IDELAYCTRL XPCI_IDC2 (.RDY(),.REFCLK(REFCLK),.RST(REFRST)) /* synthesis syn_noprune=1 */;

VHDL

Place the following after the architecture declaration and before the begin statement.

attribute syn_noprune : boolean;

attribute syn_noprune of XPCI_IDC0 : label is true;

attribute syn_noprune of XPCI_IDC1 : label is true;

attribute syn_noprune of XPCI_IDC2 : label is true;

AR# 20897
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article