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AR# 20918

v2.2 COREGen Aurora - Standard_cc_module produces WARN_CC periods that are too short for maximum length UFC messages


General Description:

Standard_cc_module produces WARN_CC periods that are too short for maximum length UFC messages. This occurs if UFC messages are used and WARN_CC and DO_CC are generated with the standard_cc_module.


To work around this issue, you must make the following changes to prevent possible UFC/CC collisions that can occur when a long UFC message is requested close to a DO_CC event.

1. Find the declaration for prepare_count_r register in the standard_cc_module and add 2 bits:

For example,

reg [0:7] prepare_count_r; ===> reg [0:9] prepare_count_r;

signal prepare_count_r : std_logic_vector(0 to 7):="00000000"; ===> signal prepare_count_r : std_logic_vector(0 to 9):="0000000000";

2. Change the shift register code for prepare_count_r:

i. Find the line where prepare_count_r is assigned in the code.

eg. Single 2-byte lane VHDL

-- For 1 lane, we need an 8-cycle count.



if(USER_CLK'event and USER_CLK = '1') then

prepare_count_r <= (cc_idle_count_done_c & prepare_count_r(0 to 6)) after DLY;

end if;

end process;

eg Single 2-byte lane Verilog

// For simulation, initialize prepare count to all zeros to simulate an SRL16

// after configuration. The circuit will also work is the init value includes

// ones.


prepare_count_r = 8'b00000000;

// For 1 lane, we need an 8-cycle count.

always @(posedge USER_CLK)

prepare_count_r <= `DLY {cc_idle_count_done_c,prepare_count_r[0:6]};

ii. Change the count used according to the table provided on Pg. 91 of the COREGen Aurora User Guide: (http://www.xilinx.com/aurora/aurora_member/ug061.pdf).If using

Verilog, also change the initial statement to 10 bits.

3. Find every instance of prepare_count_r(7) or prepare_count_r[7] and replace with prepare_count_r(9) or prepare_count_r[9] for VHDL and Verilog respectively.

AR# 20918
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article