| AR# | 20919 |
| Topic | SW-Coregen |
| Last Modified | 2009-04-08 00:00:00.0 |
| Status | Archive |
Keywords: TEMAC, Tri-mode, Ethernet, MAC, readme, IP, Aurora, wrapper, HDL, simulation
At the end of an IP core generation, an "<IP-name>_README.txt" file is created for the new core. The README file lists the various files that were created for the core and gives the files' purpose. Does the information listed for ".v" and ".vhd" files apply to reference designs?
The README states, "Verilog (or VHDL) wrapper file provided to support functional simulation. This file contains simulation model customization data that is passed to a parameterized simulation model for the core."