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AR# 20934 7.1i ISE - "ERROR:HDLParsers:3264 - Can't read file "testbench_par.prj": No such file or directory for Post-PAR Verilog timing simulation - Fuse failed"

Description

Keywords: Simulator, place and route, VHDL, tbw, waveform, Generated Simulation Language

Urgency: Standard

General Description:
When running the Simulate Post-Place and Route Model process for a Test Bench Waveform (TBW) using the ISE Simulator, the following errors occur:

"ERROR:HDLParsers:3264 - Can't read file "<testbench_name>_par.prj": No such file or directory
ERROR: Fuse failed
Done: failed with exit code: 0004."

The following pop-up error messages may also be displayed.

"FDK Error: "Program" item for command line 'tbwTOtimesim_vhw' not specified in FDK file.
FDK Error: "Program" item for command line 'timesim_vhwTOisim_par_prj' not specified in FDK file.
Error: Sources for both VHDL and Verilog have been detected in this project. The Xilinx Simulator supports single-language simulation only."

Solution

The ISE Simulator is a single language simulator. The output simulation netlist, as well as the intermediate test bench file created for a Test Bench Waveform (TBW) file, will match the language specified by the Generated Simulation Language property. Therefore, the Generated Simulation Language selection in the Project Properties should match the project source type (Verilog or VHDL). Additionally, in 7.1i, if the Generated Simulation Language is changed after a simulation has been attempted, Project Navigator fails to reset the Generated Simulation Language to the new value.

To work around this, do the following:
1. Run Project -> Cleanup Project Files.
2. Close and re-open Project Navigator.

This problem has been fixed in the latest 7.1i Service Pack available at:
http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 7.1i Service Pack 1.

Actions

AR# 20934
Date Created
Last Updated 12/13/2006
Status Archive
Type
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