We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20951

LogiCORE PCI - VHDL PING example design delivered with the core does not complete simulation, and signals go undefined


General Description: 

When simulating the VHDL version of the PING example design delivered with the core, it does not complete and seems to hang. The waveform shows the signals go undefined after the configuration transactions.


In version 3.0.140 release of the PCI Core, the "ping.vhd" was slightly changed to include instantiated IBUFS for PING_REQUEST32 and PING_REQUEST64. However, the UniSim library declaration was not added to the "ping.vhd" file. Add the following to the top of the file under the existing library declarations: 


-- synopsys translate_off 

library UNISIM; 


-- synopsys translate_on 


This has been fixed in build 3.0.146 and greater.

AR# 20951
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article