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AR# 21002

7.1i Install - ISE Service Pack Release Notes/README


Keywords: SP1, SP2, SP3, SP4, Solaris, Linux, Windows, software, update

Urgency: Standard

General Description:
This README Answer Record contains the Release Notes for 7.1i Service Packs. The Release Notes include installation instructions and a list of the issues that are fixed. Note that ISE Service Packs are cumulative; therefore, fixes found in Service Pack 1 are also found in Service Packs 2 and 3.



A successful installation of Xilinx ISE 7.1i Service Pack "x" updates your software version number to 7.1.0xi.

- The destination directory specified during the set-up operation must contain an existing Xilinx ISE installation. Only existing files are updated. Any new device support not previously installed should first be installed from the Xilinx ISE CD before adding the Service Pack.
- You must set the XILINX environment variable before installing the Service Pack.

Installation Instructions for Windows Users
1. Download "7_1_0xi_pc.exe" from:

2. Run "7_1_0xi_pc.exe".

Installation Instructions for Red Hat Linux & Solaris Users
1. Download "7_1_0xi_<platform>.zip from:

2. Move the zip file to an empty "staging" area, and unzip the downloaded file.

For example:
mv 7_1_0xi_<platform>.zip /home/<staging_dir>
cd /home/<staging_dir>
unzip 7_1_0xi_<platform>.zip

3. Run "setup".

NOTE: WebUpdate can also be used to download the Service Pack update on Linux and Windows platforms.


**Issues Addressed in 7.1i Service Packs**


(SP4) Speeds Files - What speed files are currently installed for Virtex/-E/-II/-II Pro/-4 and Spartan-II/-IIE/-3 device families in ISE? (Xilinx Answer 12201)
(SP3) Stepping FAQ - What is a silicon stepping level? How do I determine the stepping level of a device? What do I do in Software? How do I order a certain stepping level? (Xilinx Answer 20947)
(SPx) FPGA/CPLD/PROM - What are the device/part markings for Xilinx devices? (Xilinx Answer 1067)

Virtex-4 Devices

(SP4) Virtex-4 - Where can I find silicon stepping information specific to Virtex-4 devices? (FAQs) (Xilinx Answer 21605)
(SP3) 7.1i Virtex-4, MAP - "INFO: Logic has been added to automatically put the DCM in auto-calibration mode..." (Xilinx Answer 21435)
(SP3) 7.1i, Virtex-4 - Is there a summary list of ISE design tools known issues affecting the Virtex-4 features support? (Xilinx Answer 19713)
(SP3) Virtex-4 - Speed Files Revision History (Xilinx Answer 20953)
(SP3) Virtex-4 DCM - What are the new DCM parameters that have been added to the Virtex-4 Data Sheet? (Xilinx Answer 21127)
(SP3) Virtex-4 - Where can I find silicon stepping information specific to the Virtex-4 devices ? (FAQ) (Xilinx Answer 21605)
(SP3) Virtex-4 RocketIO - Why is MGTCLK not working in hardware? (Xilinx Answer 21532)

Spartan-3E Devices

(SP4) Spartan-3E, IDDR2 - Cascaded data path is not programmed correctly in some instances (Xilinx Answer 21717)
(SP4) Spartan-3E - Input delay elements on the bottom edge are not programmed correctly (Xilinx Answer 21721)
(SP3) Spartan-3E - Are IBIS models available? (Xilinx Answer 21426)
(SP3) Spartan-3/-3E - "ERROR:BitGen - Bit files can only be generated for Engineering Silicon by enabling the -g es:<digit> BitGen option." (Xilinx Answer 21023)
(SP3) Spartan-3E, Configuration - The design does not function properly when reconfiguring through iMPACT (Xilinx Answer 21024)
(SP3) Spartan-3E - What design tools version supports the XC3S250ECP132 and XC3S500ECP132? (Xilinx Answer 21598)
(SP3) ISE 7.1i, Spartan-3E - Known Issues affecting Spartan-3E device features in the 7.1i design tools (Xilinx Answer 20813)

Architecture Wizard

(SP1) 7.1i RocketIO Wizard Virtex-4 RocketIO - Usage of GT11CLK in Architecture Wizard (Xilinx Answer 17415)


(SP4) 7.1i SP3 BitGen - Setting the -g persist option has no effect in hardware. (Xilinx Answer 21877)
(SP2) 7.1i BitGen - "Fatal Error: Bitgen: Bs_Bitgen.c: 344:" (Xilinx Answer 21282)

Constraints Editor

(SP2) 7.1i Constraints Editor - Non-clock ports are listed as Clocks and OFFSET IN/OUT are N/A (Xilinx Answer 21289)
(SP1) 7.1i SP1 Constraints Editor, Virtex-4 - Incorrect voltage range (Xilinx Answer 20978)


(SP2) 7.1i CPLD Hprep6 XC9500/XL/XV CoolRunner XPLA3 - Device (Jedec) does not function properly on the board (Xilinx Answer 21168)
(SP2) 7.1i CPLDFit CoolRunner-II - XC2C128 Timing values change in Service Pack 2 (Xilinx Answer 21266)


(SP3) 7.1i ECS - The Spartan-3E symbol library does not contain obuft4, obuft8, and obuft16 (Xilinx Answer 21539)
(SP3) 7.1i ECS - The View HDL Functional Model process for a schematic design gives "Error: Symbol Not Found: obufe4 and obufe16" (Xilinx Answer 21540)
(SP1) 7.1i ECS - Bus width of pin I and O is incorrect in symbol ICAP_VIRTEX4 (Xilinx Answer 20920)
(SP1) 7.1i ECS - "ERROR:NgdBuild:604 - STARTBUF_SPARTAN3E could not be resolved..." for schematic design (Xilinx Answer 20923)
(SP1) 7.1i ECS - BSCAN_SPARTAN3E and CAPTURE_SPARTAN3E components generate "ERROR:HDLCompilers:87" in XST (Xilinx Answer 20926)


(SP2) 7.1i Floorplanner Virtex-4 - The BUFR is displayed in the incorrect column (Xilinx Answer 21290)
(SP1) 7.1i Floorplanner - Cannot place FG5 or FG6 as groups (Xilinx Answer 20979)
(SP1) 6.3i SP2 Floorplanner - Write out constraints, then read them back in with errors (Xilinx Answer 20980)


(SP2) 7.1i Spartan-3E iMPACT - The design does not function properly when reconfiguring through iMPACT (Xilinx Answer 21024)


(SP2) 7.1i ISE - Synplify error - @E "filename.vhd" Cannot find library <library_name> (Xilinx Answer 21291)
(SP2) 7.1i ISE - Open State Diagram (".dia" file) from Project Navigator and StateCAD gives the error "Could not open file -instyle ise <filename>.dia" (Xilinx Answer 21281)
(SP2) 7.1i ISE - ChipScope inserter is given the wrong input netlist if called from Project Navigator when the Synplify-HDL flow is selected (Xilinx Answer 20905)
(SP2) 7.1i ISE - Error Navigation finds the correct file but does not navigate to the correct HDL line number (Xilinx Answer 20580)
(SP2) 7.1i ISE - When looking for Software Updates, no window is displayed (Xilinx Answer 20760)
(SP2) 7.1i ISE - A State Diagram (".dia" file) may be added as a user document. However, if the project is closed and reopened, the ".dia" file is no longer shown in the Project Sources window (Xilinx Answer 21279)
(SP2) 7.1i ISE - Project Navigator source selection automatically goes to the "top" level when a lower-level module is opened (Xilinx Answer 21280)
(SP2) 7.1i SP1 ISE - CORE Generator and Architecture Wizard Cores (.xco, and .xaw files) are not added as project sources in Project Navigator when created through Project -> New Source (Xilinx Answer 21070)
(SP2) 7.1i ISE - When running EDIF flow in Project Navigator, the incorrect input netlist is passed to ChipScope inserter (Xilinx Answer 20906)
(SP1) 7.1i ISE - Exiting Project Navigator on Linux 64 platform gives a Core Dump (Xilinx Answer 20927)
(SP1) 7.1i ISE - When I open a 6.xi project in ISE 7.1i, the following message occurs: "File '<source.vhd>' is already in library '<lib_name>', it cannot be added again." (Xilinx Answer 20676)
(SP1) 7.1i ISE - "ERROR:Cpld:993 - The device name 'Auto' is invalid. Please specify a correct device name" occurs during CPLD implementation (Xilinx Answer 20743)
(SP1) 7.1i ISE - The ".ise" project file is not associated to Project Navigator in Windows Explorer (Xilinx Answer 20929)
(SP1) 7.1i ISE - Known issues related to integrated Precision synthesis in Project Navigator (Xilinx Answer 20864)
(SP1) 7.1i ISE - Fuse failed for Post-PAR Verilog timing simulation (Xilinx Answer 20934)
(SP1) 7.1i ISE - "FATAL ERROR: Unable to open log file __projnav/<process_name>.err in write mode" on UNIX platform (Xilinx Answer 20862)
(SP1) 7.1i ISE - Synthesis options: The options Hierarchy Separator does not get carried over when a 6.1i project is opened in 7.1i ISE (Xilinx Answer 20675)
(SP1) 7.1i ISE - The DONE_cycle:keep option is not available in the Project Navigator GUI (Xilinx Answer 20933)
(SP1) 7.1i ISE - Synplify flow gives "Process "Synthesize" did not complete" for designs containing CORE Generator or Architecture Wizard Cores (Xilinx Answer 20761)
(SP1) 7.1i ISE - Incremental Design Flow fails ProjNav errors executing TclFileWrapper4Halite.tcl only in ID flow (H.38.2) (Xilinx Answer 20932)


(SP2) 7.1i Virtex-4 MAP - "INTERNAL_ERROR:Pack:pksbatsdesign.c:1610:1.31 - No Xdm objects for PERIOD=20000.000000 pS ..." (Xilinx Answer 21268)
(SP2) 7.1i MAP - STARTUP is incorrectly removed (Xilinx Answer 21099)
(SP2) 7.1i Virtex-II PRO MAP - Directed Routing constraints block trimming of loadless/driverless nets (Xilinx Answer 21269)
(SP2) 7.1i MAP - Crash during "Mapping design into LUTs..." phase when KEEP_HIERARCHY used (Xilinx Answer 21270)
(SP2) 7.1i Virtex-4 MAP - Post-MAP simulation problem affecting DSP48s (Xilinx Answer 21018)
(SP2) 7.1i SP1 Virtex-II MAP - "ERROR:PhysDesignRules:371- The signal <> is multisource. Signal has 3 driver pins." (Xilinx Answer 21052)


(SP1) 7.1i NGDBuild/Constraints Speed Files, Virtex-II Pro - New I/O standards (Xilinx Answer 20981)
(SP1) 7.1i NGDBuild/Constraints Speed File, Virtex-II - New I/O standards (Xilinx Answer 20982)
(SP1) 7.1i NGDBuild/Constraints Speed File, Spartan-3 - New I/O standard (Xilinx Answer 20983)
(SP1) 7.1i NGDBuild/Constraints Speed File, Virtex-4 - New I/O standard (Xilinx Answer 20984)


(SP2) 7.1i PACE Spartan-3E - The Global Clock pins are not displayed on the left or right sides (Xilinx Answer 21292)
(SP2) 7.1i PACE - The Spartan-3 SSO data does not match the data sheet (Xilinx Answer 20126)


(SP2) 7.1i Spartan-3E PAR - "ERROR:Place:311 - The IOB c is locked to site PAD107 in bank 3. This violates the SelectIO banking rules(SSTL2_I)." (Xilinx Answer 21040)
(SP2) 6.3is1PAR - "ERROR:Place:120 - There were not enough sites to place all selected components" (Xilinx Answer 20093)
(SP2) 7.1i Virtex-II PAR - Clock placer fails with invalid error (Xilinx Answer 21271)
(SP2) 7.1i Virtex-4 PAR - Placer crash in phase 8.28 during PAR or timing-driven MAP (Xilinx Answer 21272)
(SP2) 7.1i Virtex-4 PAR - "ERROR:Place:604 - Placer was unable to create LVDS pair for component ..." (Xilinx Answer 21068)
(SP2) 7.1i Service Pack 2 Virtex-II Pro PAR - Local clock support has been added for Virtex-II Pro MGTs (Xilinx Answer 21273)


(SP2) 7.1i PrimeTime Script - xp_clock_latency script reduces un-annotated arc warning (Xilinx Answer 21293)


(SP3) 6.3 EDK - Virtex-4 PowerPC simulation - How to avoid "usr_pblk_adv_cap.VMC ... VMC:4355300:(S103) {SRAM1PSR_T1C00512X132D04S1} CCLK is at X state. Cell corrupted." warnings (Xilinx Answer 21197)
(SP3) LogiCORE SPI-4.2 (POS-PHY L4) v7.2 - Verilog SimPrim: IDELAYCTRL output (RDY) is never asserted (Xilinx Answer 21361)
(SP3) 7.1i UniSim, Simulation Virtex-4 - The write process in the Dynamic Reconfiguration does not work during a simulation of the DCM_ADV (Xilinx Answer 21242)
(SP3) Virtex-4 RocketIO - Why is MGT with GT11_MODE="B" not working correctly in VHDL simulation? (Xilinx Answer 21283)
(SP2) Virtex-4 RocketIO - Why is CLK_COR_SEQ_1_x not working correctly in simulation? (Xilinx Answer 21188)
(SP2) 7.1i SP1 Virtex-4 NetGen - The S and R value is left unconnected on the ODDR, which causes timing simulations to fail (Xilinx Answer 21008)
(SP2) 7.1i CompXLib - SmartModels are not getting compiled for VHDL and Verilog (Xilinx Answer 21003)

Speed Specs

(SP2) 7.1 Spartan-3E Speed Specs - 24-150 MHz DCM warning is incorrect frequency range for Spartan-3E DCM in Low Frequency mode (Xilinx Answer 21297)
(SP2) 7.1i Speed Spec Spartan-3E - I do not see any paths through the PCILOGICSE component (Xilinx Answer 21298)


(SP4) 7.1i SP2 Timing Analysis - Timing Report shows more paths than previous version of software (Xilinx Answer 21343)
(SP4) 7.1i SP3 Timing Analyzer/Timing - Clock Uncertainty Missing in timing report (Xilinx Answer 21966)
(SP2) 7.1i Timing Analyzer/TRCE Virtex4 - Timing analysis on Latch D -> Q as transparent latch delay when lat_d_q is disabled (Xilinx Answer 21294)
(SP1) 6.3isp3 Timing, Spartan-3 - Min/Max values switched for Timing check on DCMs (Xilinx Answer 20985)
(SP1) 6.3isp3 Timing Analyzer - Rounding errors result in large negative slack values for timing paths (Xilinx Answer 20986)


(SP3) 7.1i XPower - Power value changes when service pack is installed (Xilinx Answer 21556)
(SP3) 7.1i XPower - Virtex-4 (xc4vsx55) missing VCCAUX power estimate (Xilinx Answer 21557)
(SP1) 7.1i XPower - Supported devices are XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-4 (Xilinx Answer 12091)
(SP1) 7.1i XPower - "Error:Power:101:Spartan-3E devices are not supported in this product" (Xilinx Answer 20925)
(SP1) 7.1i XPower - "WARNING:Power:304 - No input signal found for U1_DCI/IBUFDS" (Xilinx Answer 20928)
(SP1) 7.1i XPower - LVDS quiescent power is not estimated (Xilinx Answer 20930)


(SP3) 7.1i XST - Incremental synthesis is broken (fatal error) in 7.1i XST (Xilinx Answer 21492)
(SP3) 7.1i XST - "ERROR:HDLCompilers:175 - Source file <>does not exist" (Xilinx Answer 21089)
(SP2) 7.1i XST - XST creates incorrect logic for signed multiplier (Xilinx Answer 21223)
(SP2) 7.1i XST - "ERROR:Cpld:887 - Cannot fit the design into this device. - XST cannot now fit CPLD designs that used to fit in version 6.x" (Xilinx Answer 21224)
(SP2) 7.1i XST - Incorrect logic generated by XST when Verilog part-select is used (Xilinx Answer 20922)
(SP2) 7.1i XST - XST creates incorrect logic when using the VHDL attribute 'LAST_VALUE (Xilinx Answer 21225)
(SP1) 6.1i XST - "FATAL_ERROR:Xst:Portability/export/Port_Main.h:127:1.13" (Xilinx Answer 17481)
(SP1) 6.3i XST - XST does not set the LEGACY_MODE attribute when a multiplier is used in the XtremeDSP slice (DSP48) (Xilinx Answer 20909)
(SP1) 7.1i XST - XST ignores "tristate2logic" switch in Area optimization mode (Xilinx Answer 20914)
AR# 21002
Date Created 03/16/2005
Last Updated 08/01/2007
Status Archive
Type General Article