UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 21004

Virtex-4 RocketIO - Answer Record List

Description

This Answer Record contains a list of all Xilinx Answer Records pertaining to Virtex-4 RocketIO.

Note: Updated attribute settings are available in the Engineering Silicon Attribute Settings section below.

Solution

Engineering Silicon Attribute Settings

All Answer Records listed in this section have been rolled into the RocketIO Wizard available in CORE Generator tool.

(Xilinx Answer 22477) - Virtex-4 RocketIO - Calibration Block for CES2, CES3, and CES4 FX devices
(Xilinx Answer 23481) - Virtex-4 RocketIO - TXENOOB work-around for ES4, ES4S, Production Step 0

User Guide

(Xilinx Answer 20943) - Virtex-II Pro X, Virtex-4 RocketIO - LOSSOFSYNC signal definition
(Xilinx Answer 21304) - Virtex-II Pro, Virtex-II Pro X, Virtex-4 FX RocketIO - Is there any difference in the way the TXINHIBIT signal works in the Virtex-II Pro, Virtex-II Pro X, and Virtex-4 MGTs?
(Xilinx Answer 21305) - Virtex-II Pro, Virtex-II Pro X, Virtex-4 FX RocketIO - Is there any difference in the way the TXRESET signal works in the Virtex-II Pro, Virtex-II Pro X, and Virtex-4 MGTs?
(Xilinx Answer 21317) - Virtex-4 RocketIO - What are the wait cycles before DRDY is asserted in dynamic reconfiguration for the MGT?
(Xilinx Answer 21355) - Virtex-4 RocketIO - What is the TX/RXCRCSAMECLOCK attribute in the Virtex-4 MGT CRC block?
(Xilinx Answer 21577) - 7.1isp3 Virtex-4 RocketIO - Where are the RX_LOS_THRESHOLD_INCR and RX_LOS_THRESHOLD attributes?
(Xilinx Answer 21715) - Virtex-4 RocketIO - CRC Design FAQs
(Xilinx Answer 21758) - Virtex-4 RocketIO - Do the GT11CLK_MGT and GT11CLK primitives have a REFCLK port?
(Xilinx Answer 21838) - Virtex-4 RocketIO - What are the TXCPSEL and RXCPSEL attributes?
(Xilinx Answer 21905) - Virtex-4 RocketIO - How do I use the DIGRX_SYNC_MODE attribute?
(Xilinx Answer 21994) - Virtex-4 RocketIO - What is the value of the internal AC coupling capacitor and the subsequent corner frequency of the high-pass filter?
(Xilinx Answer 24656) - Virtex-4 FX RocketIO - Recommended VCODAC_INIT, CPSEL, and RXRCPADJ attribute settings

Data Sheet

(Xilinx Answer 22021) - Virtex-4 RocketIO - What is the maximum frequency of the DRP for RocketIO?

Logic Design

(Xilinx Answer 25469) - Virtex-4 RocketIO Wizard v 1.4 - GT11_INIT State Machine has an asynchronous input
(Xilinx Answer 20183) - Virtex-4 RocketIO - CES2/3 silicon exhibits problems with the TX 8b/10b status flag
(Xilinx Answer 20838) - Virtex-4 RocketIO - Can my RX and TX serial rates be different?
(Xilinx Answer 21012) - Virtex-4 RocketIO - How do I set up the MGT to initialize correctly in my design?
(Xilinx Answer 21354) - Virtex-4 RocketIO - Are there any skew requirements on TX/RXUSRCLK and TX/RXUSRCLK2?
(Xilinx Answer 22471) - Virtex-4 FX RocketIO Serial Transceivers - Static Operating Behavior
(Xilinx Answer 25469) - Virtex-4 RocketIO Wizard - GT11_INIT State Machine startup failure
(Xilinx Answer 30950) - Virtex-4 GT11 RocketIO - Reducing transmit skew through use of TXSYNC and GREFCLK
(Xilinx Answer 30951) - Virtex-4 GT11 RocketIO - Reducing receive inter-lane skew through use of RXSYNC for channel bonded applications.

Xilinx ISE and Third-Party Tools

(Xilinx Answer 17415) - 7.1i Virtex-4 RocketIO - Usage of GT11CLK in Architecture Wizard
(Xilinx Answer 21054) - Virtex-4 RocketIO - 7.1.01i PAR does not place GT11s, GT11CLKs, BUFGs and MGTCLK pins correctly
(Xilinx Answer 21436) - Virtex-4 RocketIO - Why does RocketIO Wizard generate different attribute values for clocking as compared to the Clocking Decision Tree in the RocketIO User Guide?
(Xilinx Answer 21541) - Virtex-II Pro, Virtex-II Pro X, Virtex-4 RocketIO - Synplify 8.0 - "ERROR:LIT:241 - Attribute MCOMMA_32B_VALUE on GT instance"
(Xilinx Answer 21576) - Virtex-4 RocketIO - 7.1i PAR does not allow a connection between the GT11 and BUFR
(Xilinx Answer 21603) - Virtex-4 RocketIO - 7.1is3 PAR - Unroutable design error occurs when GT11CLK drives DCM
(Xilinx Answer 22088) - Virtex-4 RocketIO - 7.1i MAP - "WARNING:PhysDesignRules:367 - The signal <DESIGN_MODULE/TXN> is incomplete"

RocketIO Wizard

(Xilinx Answer 22499) - Virtex-4 FX - RocketIO Wizard v1.0 Release Notes and Known Issues
(Xilinx Answer 22845) - Virtex-4 FX - RocketIO Wizard v1.1 Release Notes and Known Issues
(Xilinx Answer 23761) - Virtex-4 RocketIO Wizard v1.1 - Wizard fails to generate MGT designs above 4 Gb/s
(Xilinx Answer 24207) - Virtex-4 RocketIO Wizard v1.2 - After installing the 8.2 IP#2 LXT supplement, the Virtex-4 RocketIO Wizard v1.2 is not available
(Xilinx Answer 24077) - Virtex-4 RocketIO Wizard v1.2 - Mandatory Tactical Patch
(Xilinx Answer 25437) - Virtex-4 FX - RocketIO Wizard v1.5 - Release Notes and Known Issues for 9.2i IP Update 1
(Xilinx Answer 30576) - Virtex-4 RocketIO Wizard v1.6 - Release Notes and Known Issues for 10.1
(Xilinx Answer 31519) - Virtex-4 RocketIO Wizard v1.7 - Release Notes and Known Issues for 10.1 IP Update 3

Simulation

(Xilinx Answer 22773) - Virtex-4 RocketIO - Digital Simulation Considerations
(Xilinx Answer 21141) - Virtex-4 RocketIO - Why do I see data on the upper bytes of RXDATA with a 1 or 2-byte fabric interface width?
(Xilinx Answer 21188) - Virtex-4 RocketIO - Why is CLK_COR_SEQ_1_x not working correctly in simulation?
(Xilinx Answer 21283) - Virtex-4 RocketIO - Why is MGT with GT11_MODE="B" not working correctly in VHDL simulation?
(Xilinx Answer 21331) - Virtex-II Pro, Virtex-II Pro X, Virtex-4 RocketIO - # Attribute Syntax Error: "The Attribute ALIGN_COMMA_MSB on GT* instance *.gt*_1 is set to 0 0. Legal values for this attribute are TRUE or FALSE"
(Xilinx Answer 21352) - Virtex-4 RocketIO - Can Out of Band (OOB) Signaling be simulated in digital simulation? Can the effect of TXENOOB and RXSIGDET be seen in digital simulation?
(Xilinx Answer 21353) - Virtex-4 RocketIO - Do I have to issue a PMARESET if I change the selects on the clock multiplexers using the TX/RXCLKMODE attributes?
(Xilinx Answer 21356) - Virtex-II Pro X, Virtex-4 RocketIO - Why does the Virtex-4 MGT not channel bond?
(Xilinx Answer 21746) - Virtex-4 RocketIO - Why is there skew on the TXP/TXN signals between A and B MGTs in simulation?
(Xilinx Answer 22050) - Virtex-4 RocketIO - Why does a Fatal Error occur when I simulate the MGT in ModelSim 6.1?
(Xilinx Answer 22081) - Virtex-4 RocketIO - Can I simulate the TXSYNC/RXSYNC functionality in digital simulation?
(Xilinx Answer 23511) - Virtex-4 RocketIO SmartModel v8.1 - RXRECCLK is unstable in simulation
(Xilinx Answer 23512) - Virtex-4 RocketIO SmartModel v8.1 - TX serial data is skewed between MGTs in simulation

Board

(Xilinx Answer 19699) - Virtex-II Pro, Virtex-II Pro X, Virtex-4 FX RocketIO - Board Debug Steps
(Xilinx Answer 21007) - Virtex-4 RocketIO - Why is the RX/TXPCSHCLKOUT not working in hardware?

Biasing, Power Supply and Filtering

(Xilinx Answer 20816) - Virtex-4 RocketIO - Do I have to power and/or filter unused MGTs?
(Xilinx Answer 21246) - Virtex-4 RocketIO - Why are the on-package 0.22uF bypass capacitors not included for FX MGT packages?
(Xilinx Answer 21739) - Virtex-4 RocketIO - Voltage regulator recommendations

Standards

(Xilinx Answer 21142) - Virtex-4 RocketIO- Does the Virtex-4 RocketIO support PAM-5 signaling such as is used in 1000 Base-T?
(Xilinx Answer 21763) - Virtex-4 RocketIO - SONET FAQs

AR# 21004
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-4 FX
  • Virtex-II Pro
  • Virtex-II Pro X