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AR# 21008

7.1i Service Pack 1 NetGen, Timing Simulation Virtex-4 - The S and R value is left unconnected on the ODDR, which causes timing simulations to fail


Keywords: SimPrim, ERROR, ModelSim, NC-VHDL, NC-Verilog, VCS

Urgency: Standard

General Description:
When performing a timing simulation in ISE 7.1i Service Pack 1, the ODDR does not function correctly and there are only Xs at the output.


This problem has been fixed in the latest 7.1i Service Pack available at:
The first service pack containing the fix is 7.1i Service Pack 2.
AR# 21008
Date Created 09/04/2007
Last Updated 11/16/2008
Status Archive
Type General Article