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AR# 21045

LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII v6.0 Core - Release Notes and Known Issues for the Ethernet 1000BASE-X PCS/PMA or SGMII Core


General Description:

This Answer Record contains the Release Notes for the LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII v6.0 Core, released in 7.1i IP Update #1 and included in 7.1i IP Update #2 and 7.1i IP Update #3, which includes the following:

- New Features in v6.0

- Bug Fixes in v6.0

- Known Issues in v6.0

NOTE: No updates or modifications were made to the Ethernet 1000BASE-X PCS/PMA or SGMII v6.0 Core as a result of 7.1i IP Update #2 or IP Update #3; thus, the information included below still applies to 7.1i IP Update #1, IP Update #2, and IP Update #3.

For installation instructions and design tools requirements, see (Xilinx Answer 21019).


New Features in v6.0

- Added support for ISE 7.1i.

- SGMII and 1000BASE-X support added for Virtex-4 RocketIO.

- Added support for Spartan-3E (TBI configuration only).

- New UniSim-based functional models (VHDL or Verilog) for faster simulations.

- The Transmitter Elastic Buffer has been moved out of the core into the HDL example design to allow for greater flexibility.

- Directory structure updated to support CORE Generator 7.1i.

Bug Fixes in v6.0

- CR 196782: Verilog demonstration testbench (demo_tb.v) used incorrect array sizes that cause only a portion of the frames to be transmitted and received.

- CR 196782: Incorrect alignment when "MGT CRC Enabled" is used results in incorrect IDLE generation.

Known Issues in v6.0

1. Spartan-3E support has been reinstated for all speed grade devices. Originally, all Spartan-3E support was withdrawn because it was not possible to meet the 2 ns setup and 0 ns hold I/O timing as defined in the IEEE 802.3-2002 specification using the latest Spartan-3E speed files at the time. The Spartan-3E -4 and -5 speed grade files have improved enough to where the I/O timing can now be met.

2. Simulation fails in 7.1i Service Pack 3 because RX_LOS_INVALID_INCR and RX_LOS_THRESHOLD signals are missing from SmartModel. For more information on this issue, see (Xilinx Answer 21648). To resolve this issue, install the patch below and regenerate the core.

3. 7.1i Service Pack 3 or later needs to be used when using the 1000BASE-X PCS/PMA or SGMII (not TBI) versions on Virtex-4.

4. When targeting the core with configurations that use DCMs to Virtex-4 devices, new DCM timing parameters need to be considered which might require the use of the DCM_STANDBY macro. For more information, refer to (Xilinx Answer 21882).

5. A Calibration Block for the Virtex-4 RocketIO must be used with ES devices. Refer to the Calibration Block User Guide (UG090) or contact your FAE for more details and instructions on how to connect the module to the MGTs DRP and other ports. The MGTs in the XAUI Core are instantiated in the "transceiver.v/.vhd" file. This file can be modified to instantiate GT11 Calibration Block.

6. The implementation script does not generate bitstreams for the Example Design if the target device is Spartan-3E. For more information, refer to (Xilinx Answer 21056).

7. An issue exists with the core when it is targeted to a Spartan-3E device with the TBI Interface, Management Interface enabled, and Auto-Negotiation enabled. This is the only configuration of the core that is affected. The problem is that even though the design passes static timing analysis, it fails in simulation with a hold error. This is not a core issue; it is a problem with NetGen in 7.1i Service Pack 2 that will be fixed in a future release.


To resolve issue #2 from above, apply the following patch to the Xilinx ISE installation with 7.1i Service Pack 3 and IP Update #1 or later:

NOTE: If 7.1i IP Update #1 was installed followed by this patch and then 7.1i IP Update #2 or IP Update #3 was installed, the patch will need to be reinstalled because IP Update #2 and IP Update #3 will overwrite the existing patched files with the original incorrect ones.

Install the patch as follows:

1. Extract the contents of the ".zip", ".gtar,gz", or "tar.gz" archive to the root directory of the Xilinx installation. Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure pre-defined in the archive.


Determine the Xilinx installation directory by entering the following at the command prompt:

"echo %XILINX%"

UNIX or Linux

Determine the Xilinx installation directory by typing the following:

"echo $XILINX"

NOTE: You might need to have system administrator privileges to install the patch.

2. After installing the patch, regenerate the LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII v6.0 Core from CORE Generator. The core and supporting files produced will contain the fixes mentioned above.

AR# 21045
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article