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AR# 21046

LogiCORE 10 Gigabit Ethernet MAC v6.0 Core - Release Notes and Known Issues for the 10 Gigabit Ethernet MAC Core

Description

General Description: 

This Answer Record contains the Release Notes for the LogiCORE 10 Gigabit Ethernet MAC v6.0 Core, released in 7.1i IP Update #1 and included in 7.1i IP Update #2 and 7.1i IP Update #3, which includes the following: 

 

- New Features in v6.0 

- Bug Fixes in v6.0 

- Known Issues in v6.0  

 

NOTE: No updates or modifications were made to the 10 Gigabit Ethernet MAC v6.0 Core as a result of 7.1i IP Update #2 or IP Update #3; thus, the information included below still applies to 7.1i IP Update #1, IP Update #2, and IP Update #3. 

 

For installation instructions and design tools requirements, see (Xilinx Answer 21019).

Solution

New Features in v6.0 

 

- Added support for ISE 7.1i 

- Directory structure updated to support CORE Generator 7.1i 

- New UniSim-based functional models (VHDL or Verilog) for faster simulations 

- New Local Link FIFO added to Example Design, replacing the previously supplied loopback-only FIFO 

- Simulation scripts updated to support functional simulation 

- Enhanced User Guide with additional information on: 

* Timing relationship between the bytes_valid bit in the statistics vector and the incoming frame 

* Function of the address register (contents are configured with the PAUSE frame addresses only) 

* Simplex mode limitations 

 

Bug Fixes in v6.0 

 

- CR 197487: MTI compile error on fifo.vhd Design Example model: "** Error: fifo.vhd(533): Length of actual is 9. Length of expected is 10." 

- CR 199183: Remove LVCMOS25 setting from all non-XGMII ports in the UCF file (these are no longer required) 

 

Known Issues in v6.0 

 

1. The transmitter can lock up if pause_req or tx_start is asserted while transmitter is disabled. For more information on this issue, see (Xilinx Answer 21662). To resolve this issue, install the patch below and regenerate the core. 

 

2. The Example Design FIFO can lock up when short frames are passed into it. For more information on this issue, see (Xilinx Answer 21663). To resolve this issue, install the patch below and regenerate the core. 

 

3. When targeting the core with configurations that use DCMs to Virtex-4 devices, new DCM timing parameters need to be considered which might require the use of the DCM_STANDBY macro. For more information, refer to (Xilinx Answer 21884)

 

Patch 

 

To resolve issues #1 and #2 from above, apply the following patch to the Xilinx ISE installation with 7.1i IP Update #1 or later: 

 

http://www.xilinx.com/txpatches/pub/swhelp/ip_updates/xgm_v6_0_patch1.zip
http://www.xilinx.com/txpatches/pub/swhelp/ip_updates/xgm_v6_0_patch1.tar.gz
http://www.xilinx.com/txpatches/pub/swhelp/ip_updates/xgm_v6_0_patch1.gtar.gz
 

NOTE: If 7.1i IP Update #1 was installed followed by this patch and then 7.1i IP Update #2 or IP Update #3 was installed, the patch will need to be reinstalled because IP Update #2 and IP Update #3 will overwrite the existing patched files with the original incorrect ones. 

 

Install the patch as follows: 

1. Extract the contents of the ".zip", ".gtar,gz", or "tar.gz" archive to the root directory of the Xilinx installation. Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure pre-defined in the archive.  

 

PC 

Determine the Xilinx installation directory by entering the following at the command prompt: 

"echo %XILINX%" 

 

UNIX or Linux 

Determine the Xilinx installation directory by typing the following: 

"echo $XILINX" 

 

NOTE: You might need to have system administrator privileges to install the patch.  

 

2. After installing the patch, regenerate the LogiCORE 10 Gigabit Ethernet MAC v6.0 Core from CORE Generator. The core and supporting files produced will contain the fixes mentioned above.

AR# 21046
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article