This Answer Record contains the Release Notes for the LogiCORE XAUI v6.0 Core, released in 7.1i IP Update #1 and included in 7.1i IP Update #2 and 7.1i IP Update #3, which includes the following:
- New Features in v6.0
- Bug Fixes in v6.0
- Known Issues in v6.0
NOTE: No updates or modifications were made to the XAUI v6.0 Core as a result of 7.1i IP Update #2 or IP Update #3; thus, the information included below still applies to 7.1i IP Update #1, IP Update #2, and IP Update #3.
For installation instructions and design tools requirements, see (Xilinx Answer 21019).
New Features in v6.0
- Added support for Virtex-4
- Added support for ISE 7.1i
- New UniSim-based functional models (VHDL or Verilog) for faster simulations
- Directory structure updated to support CORE Generator 7.1i
Bug Fixes in v6.0
Known Issues in v6.0
1. Simulation fails in 7.1i Service Pack 3 because RX_LOS_INVALID_INCR and RX_LOS_THRESHOLD signals are missing from Virtex-4 SmartModel. For more information on this issue, see (Xilinx Answer 21869). To resolve this issue, install the patch below and regenerate the core.
2. The core fails in PAR with 7.1i Service Pack 3 or later because of the way Virtex-4 GT11_MODE attributes are now handled. For more information on this issue, see (Xilinx Answer 21852). To resolve this issue, install the patch below and regenerate the core.
3. A patch must be used prior to 7.1i Service Pack 4 that fixes an issue with the Virtex-4 GT11 SmartModel. For more information on this patch, see (Xilinx Answer 21746).
4. A Calibration Block for the Virtex-4 RocketIO must be used with ES devices. Please refer to UG090: Calibration Block User Guide or contact your FAE for more details and instructions on how to connect the module to the MGTs DRP and other ports. The MGTs in the XAUI core are instantiated in the "transceivers.v/.vhd" file. This file can be modified to instantiate and connect the DRP module.
5. When targeting the core with configurations that use DCMs to Virtex-4 devices, new DCM timing parameters need to be considered which might require the use of the DCM_STANDBY macro. For more information, refer to (Xilinx Answer 21885).
6. The "transceviers.v(hd)" files contain incorrect GT11 attributes when the core is targeted to Virtex-4 devices. For more information and details on how to work around this, refer to (Xilinx Answer 22336).
7. An updated version of the XAUI User Guide is available within the Product Lounge that shows the updated clocking scheme incorporated into patch below. The new clocking scheme has the 156.25 MHz clock coming from TXOUTCLK rather than directly from the MGTCLK block. This was a minor change that was needed to work around a PAR issue that prevented the FPGA fabric from being clocked directly by the MGTCLK clock. The XAUI User Guide is available at:
To resolve issues #1 and #2 from above, apply the following patch to the Xilinx ISE installation with 7.1i Service Pack 3 and IP Update #1 or later:
NOTE: If 7.1i IP Update #1 was installed followed by this patch and then 7.1i IP Update #2 or IP Update #3 was installed, the patch will need to be reinstalled because IP Update #2 and IP Update #3 will overwrite the existing patched files with the original incorrect ones.
Install the patch as follows:
1. Extract the contents of the ".zip", ".gtar,gz", or "tar.gz" archive to the root directory of the Xilinx installation. Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure pre-defined in the archive.
Determine the Xilinx installation directory by entering the following at the command prompt:
UNIX or Linux
Determine the Xilinx installation directory by typing the following:
NOTE: You might need to have system administrator privileges to install the patch.
2. After installing the patch, regenerate the LogiCORE XAUI v6.0 Core from CORE Generator. The core and supporting files produced will contain the fixes mentioned above.