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AR# 21050

7.1i XST - XST removes block with no outputs, legitimate module

Description

Keywords: black, box, empty, instantiate, lower, level, inputs, optimize

When instantiating a lower level module that has inputs and no outputs (a STARTUP_VIRTEXx or ICAP_VIRTEXx for example), XST does not retain them and optimizes them away.

Solution

To work around this issue, you can create a dummy output port on that module and place a keep constraint on the port as shown in the following examples:

VHDL

entity no_outputs
port (a, b : in std_logic;
dummy : out std_logic);

attribute keep : string;
attribute keep of dummy : signal is "true";

end entity;
:
:


Verilog

module no_outputs (a, b, dummy);
input a, b;
output dummy;
//synthesis attribute keep dummy "true"
:
:


This issue is fixed in ISE 8.1i.
AR# 21050
Date Created 09/04/2007
Last Updated 01/07/2009
Status Archive
Type General Article