Urgency: Hot
General Description:
A problem was introduced in 7.1i SP1 that will cause a design to have false DRC errors if there are bi-directional I/O on hierarchy boundaries.
"ERROR:Pack:1642- Errors in physical DRC
ERROR:PhysDesignRules:371- The signal <> is multisource. Signal has 3 driver pins."
This problem has been fixed in the latest 7.1i Service Pack available at:
http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 7.1i Service Pack 2.
Meanwhile, a tactical patch is available.
Windows:
http://www.xilinx.com/txpatches/pub/swhelp/ise7_updates/71isp1_map_win_21052.zip
To install, unzip in the XILINX install directory while maintaining directory
structure.
Linux:
http://www.xilinx.com/txpatches/pub/swhelp/ise7_updates/71isp1_map_lin_21052.tar.gz
To install:
cd $XILINX
tar zxvf 71isp1_par_lin_21052.tar.gz
Solaris:
http://www.xilinx.com/txpatches/pub/swhelp/ise7_updates/71isp1_map_sol_21052.tar.gz
To install:
cd $XILINX
gzip -d 71isp1_par_sol_21052.tar.gz
tar xvf 71isp1_par_sol_21052.tar