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AR# 21075

11.1 EDK - Achieving full performance with the Virtex-4 PowerPC405 devices using the Xilinx GNU Compiler


To achieve the maximum PPC405 Processor Core operating frequency of 400 MHz for the -11 speed grade and 350 MHz for the -10 speed grade, a change must be made to the GNU compiler supplied by Xilinx.

NOTE: You can find the maximum operating frequency of the processor block when using the APU in the "Virtex-4 Data Sheet: DC and Switching Characteristics." Refer to the PowerPC Switching Characteristics section. You can access this data sheet at:


Note that using the APU controller does not affect the FCM interface clock ratio. Refer to the PowerPC 405 Processor Block Reference Guide, page 38, for more information.

Device Information

- The affected devices are Virtex-4 FX devices, including FX12, FX20, FX60 device family members with Processor Version Register (PVR) 0x20011430

- This issue does not occur in FX100, FX40, FX140, or devices with PVR 0x20011470

- For more information, see the "Processor Version Register (PVR) Interface (Virtex-4-FX Only)" section of the PowerPC 405 Processor Block Reference Guide located at:


For other processor block errata and operational guidelines, refer to (Xilinx Answer 20658).


All software compilation requires that the -mv4fxtuning option is provided to the powerpc-eabi-gcc. From XPS GUI, the following two steps are required:

- Add -mv4fxtuning to the "Extra Compiler Options" in the Software Platforms Settings (Processors, Driver Parameters and Interrupt Handlers Tab) dialog.

- Add -mv4fxtuning to the "Program Sources Compiler Options" in the Compiler Options (Advanced Tab) dialog.


- The addition of these options increases code size and run time because the new assembler inserts a "No op" between two consecutive loads.

- If compiling assembly programs by invoking the powerpc-eabi-as assembler program, the -v4fxtuning switch must be applied.

- NOPS is inserted between every two back-to-back loads, and in between explicitly hand-coded assembly routines. Consequently, any assumptions on code segment sizes must be carefully reviewed.

If you use a compiler other than the Xilinx GNU compiler, the maximum PPC405 Processor Core operating frequency is 350 MHz for the -11 speed grade and 300 MHz for the -10 speed grade.

AR# 21075
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article