This problem occurs because the PRJ file is not written out correctly. Open the PRJ file ("top.prj" in this case) and note the incorrect locations to these Verilog files:
verilog work "mem1.v"
verilog work "mem2.v"
To solve this issue, change to the following correct locations:
verilog work "../IP/mem1.v"
verilog work "../IP/mem2.v"
You can also simply copy these files to the root project directory.
This problem has been fixed in the latest 7.1i Service Pack available at:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jspThe first service pack containing the fix is 7.1i Service Pack 3.