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AR# 21096

7.1i Timing/Constraints - OFFSET IN for Virtex-4 DDR designs with regional clocks does not analyze FALLING edge groups (WARNING:ConstraintSystem:58)

Description

Urgency: Hot

General Description:

When using 7.1isp1, there are no paths analyzed for my OFFSET IN BEFORE on my falling edge FFs. The Falling identifier does not work for Virtex-4 DDR components, such as the ISERDES and IFD with regional clocks to feed the DDR components.

The normal constraint method of:

NET "Clk" TNM = CLK_GRP1;

TIMEGRP RISING_GRP = RISING RXCLK_GRP1;

TIMEGRP FALLING_GRP = FALLING RXCLK_GRP1;

OFFSET = IN 0 ns VALID 2.5 ns BEFORE "ClkIn" TIMEGRP RISING_GRP;

OFFSET = IN -2.5 ns VALID 2.5 ns BEFORE "ClkIn" TIMEGRP FALLING_GRP;

results in no items analyzed for the falling group. This message is received in implementation:

"WARNING:ConstraintSystem:58 - Constraint <TIMEGRP FALLING_GRP = FALLING TIMEGRP "CLK_GRP1";> [.\v4_ddr_opp_bufr.pcf(25)]: FALLING(TimeGrp "CLK_GRP1") does not match any design objects. One can modify the PCF to create two time groups of rising and falling registers on a BEL basis such as: TIMEGRP CLK_GRP1 = BEL "IDDR_inst1/FF0" BEL "IDDR_inst0/FF0"; TIMEGRP CLK_GRP2 = BEL "IDDR_inst1/FF1" BEL "IDDR_inst0/FF1"; OFFSET = IN 0 ns VALID 2.5 ns BEFORE COMP "ClkIn" TIMEGRP RXCLK_GRP1; OFFSET = IN -2.50 ns VALID 2.5 ns BEFORE COMP "RxClkIn" TIMEGRP RXCLK_GRP2; "

There seems to be no way to do this via UCF constraints. How can I work around this problem?

Solution

To work around this issue, you will need to create timing groups based on the instance name of each FF, rather than using the Rising and Falling Keywords. Below is a PCF example:

**************************************************************************

//!

//! FF0 is the rising edge FF

//! FF1 is the falling edge FF

//!

**************************************************************************

TIMEGRP RXCLK_GRP1 = BEL "IDDR_inst1/FF0" BEL "IDDR_inst0/FF0";

TIMEGRP RXCLK_GRP2 = BEL "IDDR_inst1/FF1" BEL "IDDR_inst0/FF1";

OFFSET = IN 0 ns VALID 2.5 ns BEFORE COMP "RxClkIn" TIMEGRP RXCLK_GRP1;

OFFSET = IN -2.5 ns VALID 2.5 ns BEFORE COMP "RxClkIn" TIMEGRP RXCLK_GRP2;

Below is a UCF example:

**************************************************************************

//!

//! FF0 is the rising edge FF

//! FF1 is the falling edge FF

//!

**************************************************************************

INST "IDDR_inst1/FF0" TNM = RXCLK_GRP1;

INST "IDDR_inst0/FF0" TNM = RXCLK_GRP1;

INST "IDDR_inst1/FF1" TNM = RXCLK_GRP2;

INST "IDDR_inst0/FF1" TNM = RXCLK_GRP2;

OFFSET = IN 0 ns VALID 2.5 ns BEFORE "RxClkIn" TIMEGRP RXCLK_GRP1;

OFFSET = IN -2.5 ns VALID 2.5 ns BEFORE "RxClkIn" TIMEGRP RXCLK_GRP2;

If you are using the ISERDES of DDR, then you can work around the problem by using the HIGH and LOW Keywords. HIGH or LOW indicates whether the first pulse is to be High or Low.

For example:

NET "Clk" TNM = CLK_GRP1;

TIMESPEC "TS_CLK1" = PERIOD 20 ns HIGH;

# For the rising and falling Edge FFs under one constraint.

OFFSET = IN 2.5 ns VALID 2.5 ns BEFORE "ClkIn" TIMEGRP CLK_GRP1 LOW;

Using a Period constraint with the HIGH Keyword and an Offset with a LOW Keyword, the Clock arrival times for the falling edged FFs are reset to account for the falling edge clock period.

AR# 21096
Date Created 09/04/2007
Last Updated 01/18/2010
Status Archive
Type General Article