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AR# 21134: MIG ML461 - DDR2 interface has both Chip Selects tied together for a dual rank DDR1/DDR2 DIMM (DDR2_DIMM_BY0_7_CS_N)
MIG ML461 - DDR2 interface has both Chip Selects tied together for a dual rank DDR1/DDR2 DIMM (DDR2_DIMM_BY0_7_CS_N)
Looking at the schematic that comes on the CD with the ML461 demo board, I noticed that on the DDR1 and DDR2 DIMM interfaces the chip selects for different ranks on the DIMMs are tied together. Can I use a dual rank DDR1/DDR2 DIMM? If so, how does this work?
A dual rank DDR1/DDR2 DIMM can be used. Xilinx has tested both single and dual rank unbuffered DDR DIMMs on the same ML461 board, and there were no differences in performance (max clock frequency). However, with a dual rank DIMM during a write operation, the same data will be written to both ranks. Also, during a read, the two chips will drive the data causing bus contention. Since the data being read is the same (since it was written the same), there is no true Pwr/Gnd bus contention except for the time difference of Clk-2-Out for the two ranks.
The recommendation would be to use a single rank DDR1/DDR2 DIMM (i.e., MT9HTF3272AG). Then, the bus contention can be avoided.