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AR# 21137

LogiCORE SPI-4.2 (POS-PHY L4) v6.2 - Is SPI4.2 v6.2 Core compatible with ISE7.1i?

Description

General Description:

Is the SPI4.2 v6.2 Core compatible with ISE7.1i?

Solution

The v6.2 of the SPI4.2 Core is officially supported on the ISE6.3i tool, and the core cannot be generated with the ISE7.1i CORE Generator. If you already have the SPI4.2 v6.2 Core generated using CORE Generator from ISE6.3i, then it is possible to implement (translate, MAP, PAR, BitGen) the design using ISE 7.1i.

If you have SPI4.2 Core configured for Static Alignment Mode, the core will implement fine in ISE7.1i without any issue.

If you have SPI4.2 Core configured for Dynamic Alignment Mode (DPA), then use the work-around mentioned below to avoid the MAP error such as:

"ERROR:MapLib:688 - Pin CATALIN in LOCK_PINS constraint does not exist."

SPI4.2 v6.2 DPA Work-around for ISE7.1i

Unix/Linux

1. Generate the SPI-4.2 v6.2 Core in the 6.3i software (can be skipped if a core has already been generated).

2. Go to following SPI4.2 lounge:

http://www.xilinx.com/ipcenter/posphyl4/posl4mc_member/spi42_v61.htm
This is a SPI4.2 Lounge area that will require a password to access.

3. Download spi_dpa_71i.sh script and copy it to your project directory.

4. Run the script, passing the netlist name to the script:

> spi_dpa_71i.sh <component_name>_pl4_snk_top.edf

or

>./spi_dpa_71i.sh <component_name>_pl4_snk_top.edf ( "./" may be needed for your UNIX environment.)

5. Open the EDF netlist and search for "CATALIN" in the file. There should be no instances of this string remaining.

6. Your SPI4.2 design can now be implemented using ISE7.1i.

PC

1. Generate the SPI-4.2 v6.2 Core in the 6.3i software (can be skipped if a core has already been generated).

2. Download the following zip file to a temporary directory and unzip it:

http://www.xilinx.com/ipcenter/posphyl4/posl4mc_member/spi42_v61.htm
This is a SPI4.2 Lounge area that will require a password to access.

3. Copy the spi_dpa_71i.exe executable to your project directory.

4. Run the script, passing the netlist name to the script:

> spi_dpa_71i.exe <component_name>_pl4_snk_top.edf

(The script might take few minutes to complete.)

5. Open the EDF netlist and search for "CATALIN" in the file. There should be no instances of this string remaining.

6. Your SPI4.2 design can now be implemented using ISE7.1i.

AR# 21137
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article