General Description:
When using 1 or 2 byte fabric interface width, the upper 2,3,4 or 3,4 bytes respectively appear to have data on them. Why?
This behavior is inherent in the functionality of the Virtex-4 RocketIO. Below is an explanation of this behavior.
8-byte fabric interface width (User only accesses all 8 bytes)
USRCLK2 cycle 0 RXDATA[63:0]
USRCLK2 cycle 1 RXDATA[63:0]
USRCLK2 cycle 2 Same as cycle 0
USRCLK2 cycle 3 Same as cycle 1 ............
4-byte fabric interface width (User only accesses lower 4 bytes)
USRCLK2 cycle 0 32'h00000000, RXDATA[31:0]
USRCLK2 cycle 1 32'h00000000, RXDATA[31:0]
USRCLK2 cycle 2 Same as cycle 0
USRCLK2 cycle 3 Same as cycle 1 ............
2-byte fabric interface width (User only accesses lower 2 bytes )
USRCLK2 cycle 0 32'h00000000, RXDATA[31:16], RXDATA[15:0]
USRCLK2 cycle 1 32'h00000000, 16'h0000, RXDATA[31:16],
USRCLK2 cycle 2 Same as cycle 0
USRCLK2 cycle 3 Same as cycle 1 ............
1-byte fabric interface width (User only accesses lower 1 byte)
USRCLK2 cycle 0 32'h00000000, RXDATA[31:24], RXDATA[23:16], RXDATA[15:8], RXDATA[7:0]
USRCLK2 cycle 1 32'h00000000, 8'h00, RXDATA[31:24], RXDATA[23:16], RXDATA[15:8]
USRCLK2 cycle 2 32'h00000000, 8'h00, 8'h00, RXDATA[31:24], RXDATA[23:16]
USRCLK2 cycle 3 32'h00000000, 8'h00, 8'h00, 8'h00, RXDATA[31:24]
USRCLK2 cycle 4 same as cycle 0
USRCLK2 cycle 5 same as cycle 1...........