UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 21158

MIG 007 - How can I change the CAS latency to 2.5 instead of 3?

Description

Keywords: CAS, latency, 2.5, MIG, redq

The MIG documentation mentions that a CAS latency of 2.5 is supported. How do I make this change?

Solution

NOTE: The method below has not been verified in simulation or hardware.

To implement CAS latency of 2.5, it is best to move the addr and command going into the memory up by 0.5 cycles, and allow the rest of the state machine to remain the same. This is the easiest change, and it will not disturb any of the critical state machines/data read timings.

Below is a link to the files with the required changes. These files must be further verified/simulated. This ZIP file also contains a README that explains the changes in greater detail:
http://www.xilinx.com/txpatches/pub/applications/xapp/cas_latency2.zip
AR# 21158
Date Created 09/04/2007
Last Updated 04/06/2009
Status Archive
Type General Article