AR #21188 - Virtex-4 RocketIO - Why is CLK_COR_SEQ_1_x not working correctly in simulation?

Search Answers Database


 

Virtex-4 RocketIO - Why is CLK_COR_SEQ_1_x not working correctly in simulation?

AR# 21188
Part HW-Rocket_IO
Last Modified 2008-05-20 00:00:00.0
Status Active
Keywords Clock Correction

Description

Keywords: Clock Correction

Clock Correction on the CLK_COR_SEQ_1_x does not seem to be working correctly in simulation. Why is that?

Solution

This problem has been fixed in the latest 7.1i Service Pack available at:
http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 7.1i Service Pack 2.

In the meantime, you can work around this problem by switching to CLK_COR_SEQ_2_x. This affects only simulation.

 
 
Jobs Events Webcasts News Investors Feedback Legal Privacy Trademarks Sitemap
©  1994-2008 Xilinx, Inc. All Rights Reserved.