Clock Correction on the CLK_COR_SEQ_1_x does not seem to be working correctly in simulation. Why is that?
This problem has been fixed in the latest 7.1i Service Pack available at:
http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 7.1i Service Pack 2.
In the meantime, you can work around this problem by switching to CLK_COR_SEQ_2_x. This affects only simulation.