6.3i EDK, Virtex-4 PowerPC simulation - How to avoid "usr_pblk_adv_cap.VMC ... VMC:4355300:(S103) {SRAM1PSR_T1C00512X132D04S1} CCLK is at X state. Cell corrupted." warnings
Description
Keywords: EDK, 6.3, Virtex-4, PowerPC, simulation, VMC, cell, corrupted
Urgency: Standard
General Description:
When simulating a Virtex-4 based PowerPC design, numerous warnings similar to the following are outputted by the PowerPC SmartModel:
# ** Note (SmartModel):
# usr_pblk_adv_cap.VMC.VMC.VMC.VMC.VMC.VMC.VMC.VMC.VMC.VMC.VMC.VMC.VMC.VMC.VMC:4355300:(S103) {SRAM1PSR_T1C00256X046D04S1} CCLK is at X state. Cell corrupted.
# usr_pblk_adv_cap.VMC.VMC.VMC.VMC.VMC.VMC.VMC.VMC.VMC.VMC.VMC.VMC.VMC.VMC.VMC:4355300:(S103) {SRAM1PSR_T1C00512X132D04S1} CCLK is at X state. Cell corrupted.
# usr_pblk_adv_cap.VMC.VMC.VMC.VMC.VMC.VMC.VMC.VMC.VMC.VMC.VMC.VMC.VMC.VMC.VMC:4355300:(S103) {SRAM1PSR_T1C00512X132D04S1} CCLK is at X state. Cell corrupted.
How do I avoid these warnings?
Solution
These warnings have been seen when the instruction and data block RAMs of a design have not been loaded correctly in a behavioral simulation.To avoid these warnings, ensure that the instruction and data block RAMs have been loaded correctly in simulation.
This problem has been fixed in the latest 7.1i Service Pack available at:
http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 7.1i Service Pack 3.