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AR# 212

FPGA Configuration - FAST CCLK causes data frame error (INIT goes Low). What is the XC4000 CCLK frequency?


General Description:

FPGAs have optionally controlled CCLK speeds. XC4000 devices can generate a configuration clock (CCLK), used to clock configuration data to the device when operating in master mode, at two different speeds. What is the frequency range for CCLK?

If the PROM, or other memory device, cannot run at this speed then setup time requirements for configuration may be violated resulting in a failed configuration.


In the default slow mode, frequency ranges from 0.5 MHz to 1.25 MHz In FAST CCLK mode, the frequency ranges from 4 MHz to 10 MHz. The XC4000X family FPGAs can run as fast as 15 MHz in fast mode.

Return the CCLK speed to the default SLOW speed to determine if this is the cause. Consult the operating specifications for the PROM or other memory device.

AR# 212
Date Created 08/21/2007
Last Updated 12/15/2012
Status Active
Type General Article