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AR# 21213

Synplify 8.0 - Synplify combines unlike registers (FDSE, FDRE)

Description

Keywords: primitive, merges, merged, dissimilar, instantiate

Urgency: Standard

General Description:
When dissimilar register primitives are instantiated in a shift register fashion, Synplify will combine the registers to form an SRL primitive. This is logically incorrect as the FDSE has an INIT value of "1" and the FDRE has an INIT value of "0."

Solution

The only work around for now is to use Synplify version 7.7.1, as none of the synthesis directives have an affect on the design.
AR# 21213
Date Created 04/12/2005
Last Updated 04/24/2007
Status Archive
Type General Article