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AR# 21218

7.1i EDK - PLB/OPB DDR Cores fail to meet timing when running at 100 MHz in Virtex-4 devices

Description

Urgency: Hot  

 

General Description: 

While in 7.1i EDK/ISE, the PLB and OPB DDR Memory Controllers are unable to meet a 100 MHz timing constraint. There are nine failing paths inside the DDR Core. The following is an example of one of the paths: 

 

================================================================================ 

Timing constraint: TSCLK2CLK90_DDR_SDRAM_64Mx32 = MAXDELAY FROM TIMEGRP 

"OPB_Clk_DDR_SDRAM_64Mx32" TO TIMEGRP "Clk90_in_DDR_SDRAM_64Mx32" 2.25 ns; 

 

14 items analyzed, 9 timing errors detected. (9 setup errors, 0 hold errors) 

Maximum delay is 2.660ns. 

-------------------------------------------------------------------------------- 

Slack: -0.410ns (requirement - (data path - clock path skew + uncertainty)) 

Source: ddr_sdram_64mx32/ddr_sdram_64mx32/DDR_CTRL_I/COMMAND_STATEMACHINE_I/DQS_RST_I1 (FF) 

Destination: ddr_sdram_64mx32/ddr_sdram_64mx32/DDR_CTRL_I/IO_REG_I/DDR_DQS_REG_V4_I1/FF1 (FF) 

Requirement: 2.250ns 

Data Path Delay: 2.425ns (Levels of Logic = 0) 

Clock Path Skew: 0.000ns 

Source Clock: dlmb_port_BRAM_Clk falling at 5.000ns 

Destination Clock: clk_90_s falling at 7.500ns 

Clock Uncertainty: 0.235ns 

 

Data Path: ddr_sdram_64mx32/ddr_sdram_64mx32/DDR_CTRL_I/COMMAND_STATEMACHINE_I/DQS_RST_I1 to ddr_sdram_64mx32/ddr_sdram_64mx32/DDR_CTRL_I/IO_REG_I/DDR_DQS_REG_V4_I1/FF1 

Location Delay type Delay(ns) Physical Resource 

Logical Resource(s) 

------------------------------------------------- --------------------------------------------------------------------------- 

SLICE_X1Y172.YQ Tcko 0.286 ddr_sdram_64mx32/ddr_sdram_64mx32/DDR_CTRL_I/dqs_rst<1> 

ddr_sdram_64mx32/ddr_sdram_64mx32/DDR_CTRL_I/COMMAND_STATEMACHINE_I/DQS_RST_I1 

OLOGIC_X0Y174.SR net (fanout=1) 0.724 ddr_sdram_64mx32/ddr_sdram_64mx32/DDR_CTRL_I/dqs_rst<1> 

OLOGIC_X0Y174.CLK Tosrck 1.415 fpga_0_DDR_SDRAM_64Mx32_DDR_DQS_O<1> 

ddr_sdram_64mx32/ddr_sdram_64mx32/DDR_CTRL_I/IO_REG_I/DDR_DQS_REG_V4_I1/FF1 

------------------------------------------------- --------------------------- 

Total 2.425ns (1.701ns logic, 0.724ns route) 

(70.1% logic, 29.9% route)

Solution

To resolve this timing error, an update to the PLB and OPB DDR Cores is required.  

 

The core update will be fixed in the latest EDK 8.1i. In the meantime, for additional information and a possible way to work around this problem, see (Xilinx Answer 22070).

AR# 21218
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article