AR# 21225 7.1i XST - XST creates incorrect logic when using the VHDL attribute 'LAST_VALUE'

Description
Solution

Keywords: compile, constant

XST creates incorrect logic when using the 'last_value VHDL attribute:

if H02'event and (H02='1') and (H02'LAST_VALUE = '0') then

To work around this issue, use the rising_edge function instead:

if rising_edge(H02) then

This problem has been fixed in the latest 7.1i Service Pack available at:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 7.1i Service Pack 2.

Actions

Print

AR# 21225
Date Created
Last Updated	01/07/2009
Status	Archive
Type

Feed Back

All Programmable Technologies and Devices

New Connectivity Kit for High-Bandwidth and High-Performance Applications

Mobile Access for Forums

Kintex-7 FPGA KC705 Evaluation Kit

All Programmable Technologies and Devices

AR# 21225 7.1i XST - XST creates incorrect logic when using the VHDL attribute 'LAST_VALUE'

Description

Solution

Actions