We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 21225

7.1i XST - XST creates incorrect logic when using the VHDL attribute 'LAST_VALUE'


Keywords: compile, constant

XST creates incorrect logic when using the 'last_value VHDL attribute:

if H02'event and (H02='1') and (H02'LAST_VALUE = '0') then


To work around this issue, use the rising_edge function instead:

if rising_edge(H02) then

This problem has been fixed in the latest 7.1i Service Pack available at:
The first service pack containing the fix is 7.1i Service Pack 2.
AR# 21225
Date Created 04/13/2005
Last Updated 01/07/2009
Status Archive
Type General Article