Keywords: DCM, reset, write, DRP, dynamic, configuration, NCSIM, VCS, timing
Urgency: Standard
General Description:
The write process in the Dynamic Reconfiguration does not work during a simulation of the DCM_ADV. How can I fix this problem?
To work around this issue:
Follow the Virtex-4 Configuration Guide to assert the DEN, DWE, DI and DADDR as documented.
In addition, the following steps need to be performed for the DCM RESET:
1. RST asserted for 3 CLKIN cycles.
2. RST deasserted for 1 CLKIN cycle.
3. RST asserted for 3 CLKIN cycles.
The RST needs to be deasserted as the simulation model looks for an edge on the RESET port.
This issue will be fixed in ISE 7.1i Service Pack 3.