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AR# 21294

7.1i Timing Analyzer/trce Virtex4 - Timing analysis on Latch D -> Q as transparent latch delay when lat_d_q is disabled

Description

General Description:

When I am doing timing analysis on my design, which has latches, the D->Q path is analyzed as a transparent latch delay, but the lat_d_q path tracing control is disabled. This path should be analyzed as combinatorial delay and not as a synchronous element. When is this going to be fixed?

Solution

This problem has been fixed in the latest 7.1i Service Pack available at:

http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 7.1i Service Pack 2.

AR# 21294
Date Created 09/04/2007
Last Updated 01/18/2010
Status Archive
Type General Article