AR #21299 - Spartan-3E - Speed File Revision History

AR#	21299
Part	SW-Speedfiles
Last Modified	2008-10-01 00:00:00.0
Status	Active
Keywords	updates, new, current, revised, release, changes, speed, speeds, file, files, speedsfile, speedfile

Solution

1.26 Release: Description and Explanation of Changes
- Absolute Min available
- Updated Clock Tree delays
- Updated Device Modeling

1.25 Release: Description and Explanation of Changes
- Updated PCIe Delays
- Updated DCM Delays

1.23 Release: Description and Explanation of Changes
- Updated PCIe delays
- Decreased hold times on IFF in IOB
- Updated IDELAY values

1.21 Release: Description and Explanation of Changes
- Updated BUFGMUX delays
- Updated PCIe delays
- Updated IOB delays - IBUF Delays
- Updated DCM Changes
- Fixed Hold violation on DDR paths
- Changed speed grad to PRODUCTION for all devices for -4 & -5

1.19 Release: Description and Explanation of Changes
- Updated IBUF and IFD delays
- Updated PCIe delays

1.18 Release: Description and Explanation of Changes
- 3s100e, 3s500e, and 2s1600e in speed grade -4 have a status of PRODUCTION
- Increased block RAM setup time
- Increased setup time on CE pin on SLICEL flip-flops
- Set SLICEM RAM hold time to zero
- Increased setup time on DI pins on SLICEM RAM
- Increased setup time on REV and INIT pins on SLICEL flip-flops
- Increased setup time on REV pin on IOB IFF
- Increased hold time on DIN pin on IOB IFF
- Reduced delay through the DCM component

1.17 Release: Description and Explanation of Changes
- Increased setup time on DI pins on block RAM
- Updated Multiplier delay values
- Updated DCM frequency check values

1.16 Release: Description and Explanation of Changes
- Increased delays in -4 speed grade by 4% for LUT delays
- Decreased delays in -4 speed grade by 4% for FXMUX and GYMUX delays
- Overall speed increase of about 6% over v1.13
- -5 speed grade are 15% faster than -4 speed grade


1.15 Release: Description and Explanation of Changes
- Added support for -5 speed grade
- Updated -4 and -5 speed grades to ADVANCED
- Updated setup/hold values based on measurements
- Updated DCM frequency values
- Overall values are based on measurements

1.13 Release: Description and Explanation of Changes
- Updated PCI Delay types

1.12 Release: Description and Explanation of Changes
- DCM in Low Frequency mode is 5 to 280 MHz, instead of 24 to 280 MHz
- Speed Grade -4 was changed to Advanced
- Updated setup values for Distributed RAM and Shift Registers
- Added support for PCILOGICSE components
- Added new I/O Standards and removed unsupported ones

For the current speed file versions with respect to design tool releases, see (Xilinx Answer 12201).