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AR# 21302

7.1i IP Update #1- Release Notes and Known Issues for all System Logic IP

Description


General Description:

This Release Note is for all System Logic IP cores released in 7.1i IP Update 1 and available in 7.1i IP Update 2, and contains the following:



- New Features

- Bug Fixes

- Known Issues



NOTE: No updates or modifications were made to these cores as a result of 7.1i IP Update 2; thus, the information included below still applies in IP Update 2.



For the installation instructions and design tool requirements for 7.1i IP Update 1, see (Xilinx Answer 21019).

For the installation instructions and design tool requirements for 7.1i IP Update 2, see (Xilinx Answer 21737).

Solution


ISIM Simulator Support

The ISIM pre-compiled libraries for IP cores released in 7.1i IP UPdate #1 and #2 are not available.

See (Xilinx Answer 21529)





Distributed Memory Generator v1.1



The Distributed Memory Generator v1.1 should be used in all new Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4, Spartan-II, Spartan-II/E, Spartan-3 and Spartan-3E designs wherever a distributed memory is required. This core supersedes all versions of the Distributed Memory (v7.0 and v7.1).



See (Xilinx Answer 21416) for the difference between Distributed Memory Generator and Distributed Memory LogiCOREs.



New Features in v1.1

- Supports UniSim-based VHDL or Verilog functional simulation models.



Known Issues in v1.1

- In this version, initialization of Single and Dual Port Distributed Memories is not supported.

- When generating a large Distributed Memory Generator IP, CORE Generator runs out of memory and fails to generate. See (Xilinx Answer 21393).
AR# 21302
Date Created 09/04/2007
Last Updated 07/28/2010
Status Archive
Type General Article