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AR# 21317

Virtex-4 RocketIO - What are the wait cycles before DRDY is asserted in dynamic reconfiguration for the MGT?

Description

NOTE: This Answer Record is specifically for the MGT. 

In the Virtex-4 FPGA Configuration User Guide v1.1 (Xilinx UG071), Chapter 6, Reconfiguration Techniques, Figures 6-4 and 6-5 on page 81 show an undetermined number of wait cycles from when DEN is asserted to when DRDY is asserted. 

http://www.xilinx.com/support/documentation/user_guides/ug071.pdf

Solution

For the MGT, the number of wait cycles after DEN is three (3) before DRDY is asserted.
AR# 21317
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article
Devices
  • Virtex-4 FX
  • Virtex-4 LX
  • Virtex-4 QPro/R
  • More
  • Virtex-4 SX
  • Virtex-4Q
  • Virtex-4QV
  • Less