AR #21319 - LogiCORE SPI-4.2 (POS-PHY L4) - TDat Error: Data mismatch error in timing simulation (applicable to Lite Core)
LogiCORE SPI-4.2 (POS-PHY L4) - TDat Error: Data mismatch error in timing simulation (applicable to Lite Core)
| AR# | 21319 |
| Part | Coregen POS PHY Level 4 |
| Last Modified | 2006-07-10 00:00:00.0 |
| Status | Active |
| Keywords | CORE, CORE Generator, COREGen, generator, IP, update, 8.2i, 7.1i, #1, ip4_g, hip_1, ip1_h, PL4, packet, SONET, physical, link, layer, source, synchronous, phase, alignment, sink, dynamic, static, dpa , timing, simulation, data, v8.1, v4.1 |
Description
Keywords: CORE, CORE Generator, COREGen, generator, IP, update, 8.2i, 7.1i, #1, ip4_g, hip_1, ip1_h, PL4, packet, SONET, physical, link, layer, source, synchronous, phase, alignment, sink, dynamic, static, dpa , timing, simulation, data, v8.1, v4.1
When running timing simulation with SDF on a SPI4.2 design, you might receive an indication of data mismatch.
If you are running timing simulation on a SPI4.2 Design Example, you might receive the following error:
"# TDat Error: Data Mismatch #4. Expected 000f, Received 000x. 339280 ps"
Solution
The data mismatch results from the data going to unknown "x" state. This error does not occur when using ISE7.1i sp1 (H.39). Xilinx is investigating why it occurs in sp2 (H.40) and later software.To prevent "x" from propagating in your simulation, use the "+no_notifier" option to vsim command when using ModelSim Simulator (MTI).
If you are using other simulators, consult the simulator's manual for possible ways to turn off "x" propagation.