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AR# 21321

LogiCORE SPI-4.2 (POS-PHY L4) - Timing simulation error: # ** Error: */X_ISERDES SETUP Low VIOLATION ON D WITH RESPECT TO CLK;

Description

When I run timing simulation on a SPI-4.2 design with Sink core set to Dynamic Alignment mode, I receive the following error messages:

# ** Error: */X_ISERDES SETUP Low VIOLATION ON D WITH RESPECT TO CLK;

# Expected := 1.161 ns; Observed := 1.094 ns; At : 400.849 ns

# Time: 420120 ps Iteration: 2 Instance : /pl4_demo_testbench/pl4_wrapper0/...

The above error messages are from the ModelSim Simulator. The actual messages might be different for other simulators. These messages might be received multiple times throughout the simulation.

Solution

This error message will occur during the data alignment of the Sink core (PhaseAlignComplete=0) and before the core goes in frame. During alignment, the Sink core looks for the data eye. In this process, the data bus is delayed by different amounts relative to the clock, causing setup violations. Hence, it is safe to ignore this error while PhaseAlignComplete=0. Once the alignment is complete (PhaseAlignComplete =1), this error should not occur for non-continuous dynamic alignment cores.

For other timing simulation errors, see:

(Xilinx Answer 21316) - Data mismatch on DIP2

(Xilinx Answer 21319) - Data mismatch on TDat

(Xilinx Answer 21322) - SETUP, HOLD, RECOVERY violations

Revision History

07/06/2006 - Initial Release

02/11/2009 - Updated for v8.6 core, and additional information about non-continuous alignment cores

AR# 21321
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article