AR #21322 - LogiCORE SPI-4.2 (POS-PHY L4) - Timing simulation errors: SETUP, HOLD, RECOVERY violations (also applicable to Lite Core)

Description

Keywords: CORE Generator, COREGen, IP, update, 8.2i, 7.1i, #1, ip4_g, hip_1, ip1_h, ip1_im, PL4, packet, SONET, physical, link, layer, source, synchronous, phase, alignment, sink, dynamic, static, dpa, lite, timing, simulation, error, v8.1, v4.1


When I run timing simulation on a SPI-4.2 design, the following timing violations occur:

#** Error: /var/tmp/xil_EAAyPaOfT(79698): $setup( negedge CE &&& (ce_clk_enable == 1):6902 ps, posedge CLK:7093 ps, 392 ps );
# Time: 7093 ps Iteration: 0 Instance: /pl4_demo_testbench/pl4_wrapper0/\pl4_v72_dyn_128_pl4_snk_top0/U0/core0/post0/Stage2Data_128\

# ** Error: /var/tmp/xil_EAAyPaOfT(3334): $hold( posedge CLK:6222347 ps, posedge I &&& (in_clk_enable == 1):6222532 ps, 332 ps );
# Time: 6222532 ps Iteration: 0 Instance: /pl4_demo_testbench/pl4_wrapper0/\pl4_v72_dyn_128_pl4_snk_top0/U0/clkdomain0/srts/output_ff\

# ** Error: /var/tmp/xil_EAAyPaOfT(3337): $recovery( negedge RST:106519 ps, posedge CLK &&& (rst_clk_enable == 1):106920 ps, 575 ps );
# Time: 106920 ps Iteration: 1 Instance: /pl4_demo_testbench/pl4_wrapper0/\pl4_v72_dyn_128_pl4_snk_top0/U0/core0/queue0/rwr0/state_FFd2_15478\

# Time: 1525824332 ps Iteration: 0 Instance: /pl4_demo_testbench/pl4_wrapper0/\pl4_v72_dyn_128_pl4_src_top0/U0/core0/fifo0/PL4_Source_FIFO/reg_xfr_addr_gray/reg_gray_addr2\
# ** Error: /var/tmp/xil_EAAyPaOfT(3334): $hold( posedge CLK:1525829061 ps, posedge I &&& (in_clk_enable == 1):1525829320 ps, 332 ps );