We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 21333

7.1i Install - EDK Service Pack Release Notes/README


Keywords: SP1, SP2, SP3, Solaris, Linux, PC, software, update

Urgency: Standard

General Description:
This README Answer Record contains the Release Notes for 7.1i Service Packs.

The Release Notes include installation instructions and a list of the issues that have been fixed. Note that ISE Service Packs are cumulative; therefore, fixes found in Service Pack 1 are also found in Service Packs 2.

Note: EDK 7.1i SP2 REQUIRES ISE 7.1i SP3



A successful installation of Xilinx EDK 7.1i Service Pack "x" updates your software version number to 7.1.0xi.

1. The destination directory specified during the set-up operation must contain an existing Xilinx EDK installation. Only existing files are updated.
2. You must set the XILINX and XILINX_EDK environment variables before installing the Service Pack.

Installation Instructions for Windows Users
1. Download "EDK_7_1_0xi_win.exe" from:
2. Run "EDK_7_1_0xi_win.exe"

Installation Instructions for Red Hat Linux & Solaris Users
1. Download "EDK_7_1_0xi_<platform>.zip from:
2. Move the zip file to an empty "staging" area, and unzip the downloaded file.

For example:
mv EDK_7_1_0xi_<platform>.zip /home/<staging_dir>
cd /home/<staging_dir>
unzip EDK_7_1_0xi_<platform>.zip

3. Run "setup"


Issues Fixed by 7.1i Service Packs

(SP1) 6.3 EDK - PlatGen - Verilog `include compile directive in pcore not supported (Xilinx Answer 21334)

(SP1) 7.1 EDK - PlatGen - C_MASK for multiple LMB peripherals incorrectly generated (Xilinx Answer 21336)

(SP2) 7.1 EDK - The LwIP library does not use the compiler settings from LibGen (Xilinx Answer 21655)

(SP1) 7.1 EDK - LibGen does not work properly with Cygwin 1.5-13 (Xilinx Answer 21157)

(SP1) 7.1 EDK - Running LwIP with Virtex-4 devices generates "ERROR FROM TCL:- lwip () - unknown processor type ppc405_virtex4" (Xilinx Answer 21123)

(SP2) 7.1 EDK - GNU - The MicroBlaze GNU Compiler provides incorrect usage of unsigned division instruction (Xilinx Answer 21656)

(SP2) 7.1 EDK - GDB issues the following error: "Internal error: pc 0x1020 in read in psymtab, but not in symtab." (Xilinx Answer 21589)

(SP2) 6.3 EDK - GPIO v2.00.a software driver fails in Linux (Xilinx Answer 20355)

(SP1) 7.1 EDK - New linker script file not listed in Applications tab (Xilinx Answer 21335)

(SP1) 7.1 EDK - GNU - MB-GCC problem with long constants in 7.1.0 (Xilinx Answer 21337)

(SP1) 7.1 EDK - GNU - The mb-gcc issues with fprintf and floating point values (Xilinx Answer 21342)

(SP1) 7.1 EDK - GNU - mb-gcc - abs() function does not word align (Xilinx Answer 21265)

(SP1) 7.1 EDK - Achieving full performance with the Virtex-4 PowerPC405 devices using the Xilinx GNU Compiler (Xilinx Answer 21075)

(SP2) 7.1i EDK - XMD does not auto-detect a Spartan-3E device (Xilinx Answer 21674)

(SP1) 7.1i/6.3i EDK - XMD debug options cannot be set if peripheral repository directory is used (Xilinx Answer 21219)

(SP1) 7.1i EDK - XMD does not connect to PowerPC in FX40 and FX60 devices (Xilinx Answer 20296)

(SP1) 7.1i EDK - ACE file generation fails/unable to connect to target when using "genace.tcl" on a PC (Xilinx Answer 21220)

(SP1) 7.1i EDK - XMD - Platform Studio XMD Debug Options box does not have an option for USB cable (Xilinx Answer 21338)

(SP1) 6.3 XMD - MicroBlaze FSL fastdownload link is slow in Virtex-4 (Xilinx Answer 20807)

(SP1) 6.3 EDK - Base System Builder (BSB) generated UCF constraints do not follow XILINX recommended syntax (Xilinx Answer 20896)

(SP1) 7.1 EDK - BSB sets wrong parameter values for plb_emc (Xilinx Answer 21339)

(SP2) 7.1i EDK - Certain MicroBlaze 4.0 cache link (XCL) sizes create errors during PAR (Xilinx Answer 21675)

(SP2) 7.1i EDK - MicroBlaze 4.00.a Barrel Shifter option produces incorrect results (Xilinx Answer 21676)

(SP2) 7.1i EDK - An EDK design with a floating point unit (FPU) fails in Virtex, Virtex-E, Spartan-II and Spartan-IIE (Xilinx Answer 21677)

Processor IP
(SP2) 7.1i EDK SP2 - plb_ddr 1.10a hard to meet timing in Virtex-4 (Xilinx Answer 21700)

(SP2) 7.1i EDK SP2 - DCR devices might errantly acknowledge requests when PPC has C_DCR_RESYNC=1 option (Xilinx Answer 21701)

(SP2) 7.1 EDK - plb_ipif_v2_01_a Slave attachment does not respond to IP master read when C_Burst_Enable is False (Xilinx Answer 21485)

(SP2) 7.1i EDK SP2 - PLB DDR2 might fail in timing simulation when using ASYNC FIFO 4.0 (Xilinx Answer 21706)

(SP2) 7.1i EDK SP2 - OPB GPIO V3_01_B may cause timing difficulties in a MicroBlaze or PowerPC system (Xilinx Answer 21705)

(SP2) 7.1 EDK - Processor IP Core, the XST tool in 7.1 EDK and higher is using one additional BUFG than 6.3 EDK for OPB SPI and other cores (Xilinx Answer 21569)

(SP2) 7.1i EDK SP2 - OPB_PCI core has errors in the MPD (Xilinx Answer 21698)

(SP2) 7.1i EDK SP2 - PLB/OPB_EMC 2.00.a 3-state registers cannot be packed into IOBs (Xilinx Answer 21699)

(SP2) 7.1i EDK SP2 - MicroBlaze Reference Guide v5.0 for the cmp and cmpu is incorrect (Xilinx Answer 21702)

(SP2) 7.1i EDK SP2 - OPB_DDR v2.00.a - incorrect range for C_DDR_DWIDTH (Xilinx Answer 21703)
AR# 21333
Date Created 04/27/2005
Last Updated 04/13/2007
Status Archive
Type General Article