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AR# 21359

LogiCORE SPI-4.2 (POS-PHY L4) v7.2 - Failing simulation in SPI-4.2 v7.2 when loading pl4_stimulus.vhd

Description

When running simulation using the VHDL demo testbench, simulation does not load successfully. The problem occurs when the user selects 511 or 512(max) for "Length of Calendar Sequence" (SrcCalendar_Len) or when the user selects or 256 (max) for "Iteration of Status Sequence Before DIP2" (SrcCalendar_M). Following is the fatal error message: 

 

 # ** Fatal: (vsim-3421) Value 512 is out of range 0 to 511. 

 # Time: 7496755 ps Iteration: 4 Process: /pl4_demo_testbench/pl4_stimulus0/#MERGED#store_status,get_status_ctl,send_status File: ../pl4_stimulus.vhd 

 # Fatal error at ../pl4_stimulus.vhd line 1247

Solution

This problem will not occur when SrcCalendar_Len of 1 to 510 is selected and when SrcCalendar_M of 1 to 255 is selected. 

 

To work around this issue, edit the "/simulation/pl4_stimulus.vhd" file and change following three sections: 

 

1) line 276 : 

 

signal LenCnt : integer range 0 to 1023; 

 

to  

 

signal LenCnt : integer range 0 to 1023 := 1; 

 

 

2) line 1228 to 1229: 

 

elsif ((LenCnt = SrcCalendar_Len + 2) and 

(MCnt = SrcCalendar_M + 1)) then 

to  

 

elsif ((LenCnt = conv_integer(SrcCalendar_Len) + 2) and 

(MCnt = conv_integer(SrcCalendar_M) + 1)) then 

 

 

3) line 1253-1254: 

 

if ((LenCnt = SrcCalendar_Len + 1) and 

(MCnt < SrcCalendar_M + 1)) then 

 

to  

 

if ((LenCnt = conv_integer(SrcCalendar_Len) + 1) and 

(MCnt < conv_integer(SrcCalendar_M) + 1)) then 

 

 

This issue has been fixed in SPI-4.2 v8.1 Core. The demonstration testbench has been updated to correct this issue.

AR# 21359
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article