AR# 21361 LogiCORE SPI-4.2 (POS-PHY L4) v7.2 - Verilog SimPrim: IDELAYCTRL output (RDY) is never asserted

Description
Solution

General Description:

When I run Verilog timing simulation, Sink Core does not go in frame and SnkOof remains High.

This issue is due to NetGen writing out the incorrect representation of the IDELAYCTRL simulation model. This issue is expected to be fixed in 7.1i Service Pack 3.

To work around this issue, use the simulator switch to turn off the transport delays:

For MTI: +transport_int_delays

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AR# 21361
Date Created	09/04/2007
Last Updated	12/15/2012
Status	Active
Type	General Article

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AR# 21361 LogiCORE SPI-4.2 (POS-PHY L4) v7.2 - Verilog SimPrim: IDELAYCTRL output (RDY) is never asserted

Description

Solution

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