We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 21362

LogiCORE SPI-4.2 (POS-PHY L4) - In Verilog timing simulation, TDat is always "0000" and no training pattern is sent


This is a pulse swallowing issue seen in the NCSIM simulator.

Use the following switch to avoid pulse swallowing issues:

NCSIM: nclab -pulse_r 10 -pulse_e 10 -pulse_int_e 10 -pulse_int_r 10
ncverilog -pulse_r/10 -pulse_e/10 -pulse_int_e/10 -pulse_int_r/10
AR# 21362
Date Created 09/04/2007
Last Updated 05/03/2010
Status Archive
Type General Article