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AR# 21399

LogiCORE PCI/PCI-X - Virtex-4 PCI 66 MHz and PCI-X 133 MHz designs fail to meet timing

Description

When I implement a PCI 66 MHz design or a PCI-X 133 MHz design, it fails to meet some of the OFFSET IN timing constraints.

Solution

Timing problems that existed for production-level devices have been corrected as of 7.1i SP4. Please download the current version of the ISE software update and obtain the current version of the PCI and PCI-X cores available in CORE Generator.

For LX and SX PCI 66 MHz and PCI-X 133 MHz designs, customers must set the device stepping level to "1" in order to meet timing. To do this, add the following to your UCF file:

CONFIG STEPPING = "1";

Xilinx has verified that the following parts with the PCI and PCI-X cores will meet timing with stepping level set to 1:

PCI Core 66 MHz

4VLX25-FF668-11

4VSX35-FF668-11

4VFX20-FF672-11

PCI Core 33 MHz

4VLX25-FF668-10

4VSX35-FF668-10

4VFX20-FF672-10

PCI-X Core 133 MHz

4VLX25-FF668-10

4VSX35-FF668-10

4VFX20-FF672-10

NOTE: PCI 66 MHz designs targeting the 4VFX20-FF672 device will also meet timing with device stepping level set to ES or 0. PCI 33 MHz constraints can be met in LX and SX SCD Step ES and Step 0 devices.

For more information on stepping levels, refer to (Xilinx Answer 21605).

It is possible to target devices other than those listed above by generating UCF files from the PCI/PCI-X UCF Generator, available through CORE Generator.

To download the latest IP Update, go to:

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp

You must verify that the generated UCF files meet the necessary timing requirements. Also, you should ensure that the stepping level is set correctly for these files, as indicated above.

The PCI Core does not support full 66 MHz operation in LX and SX SCD Step ES and Step 0 devices. For prototyping and lab environments, you may wish to use these devices, but you should be aware they will not meet all timing constraints. Most notably, these devices will fail the OFFSET IN constraints on some of the paths.

For more information on techniques to reach timing closure for PCI 66 MHz V-4 designs, please see (Xilinx Answer 22921).

AR# 21399
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article