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AR# 21411

LogiCORE Binary Counter v8.0 - Why is there a mismatch between the behavioral and timing simulation when using the THRES0?

Description

Keywords: CORE, CORE Generator, CORE Generator, DSP, mismatches

Why is there a mismatch between the behavioral and timing simulation when using the THRES0?

Solution

This will happen only when SINIT is asserted and the CE is deasserted. To avoid this situation, you should not toggle SINIT when the CE is not asserted.

This is fixed in 7.1i IP Update 2.
AR# 21411
Date Created 09/04/2007
Last Updated 04/09/2009
Status Archive
Type General Article