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AR# 21412

LogiCORE Binary Counter v8.0 - Why is there a mismatch between the behavioral and timing simulation on the Q output?

Description

Keywords: CORE, CORE Generator, COREGen, DSP, Binary Counter, LogiCORE, Q, behavioral, timing, simulation, mismatches

Urgency: Standard

General Description:
Why is there a mismatch between the behavioral and timing simulation on the Q output?

Solution

This will happen only when SINIT is asserted and the CE is deasserted. To avoid this situation, you should not toggle SINIT when the CE is not asserted.

This is fixed in 7.1i IP Update 2.
AR# 21412
Date Created 05/09/2005
Last Updated 07/12/2007
Status Archive
Type General Article