LogiCORE Distributed Arithmetic FIR (DA FIR) - Why is there a mismatch between the behavioral simulation width and the instantiation template for Interpolating Halfband filters?
Description
Keywords: COREGen, CORE Generator, DSP
Why is there a mismatch between the behavioral simulation width and the instantiation template for Interpolating Halfband filters?
For example, when I generate the DA FIR with interpolating halfband, selected the behavioral simulation model, I can see that the generic map in the wrapper file contains this line:
c_result_width => 18
It should be:
c_result_width => 19
This can be seen when you look at the instantiation template, which will have the following:
result_width std_logic_vector(18 downto 0)
Solution
To work around this issue, modify the following line in the wrapper file:c_result_width => 18
Just add "1" to the width and this will resolve the problem.
For example:
c_result_width => 19