The MAP report contains the following information:
What happens when DCM is set to auto-calibration mode? How does it affect my design?
(Xilinx Answer 21127) describes how to manually insert the DCM_STANDBY macro when CLKIN or CLKFB stops longer than the DCM_INPUT_CLOCK_STOP parameter, or when asserting DCM RST longer than the DCM_RESET parameter. The manual insertion applies to Virtex-4 LX/SX ES and Production Step 1 devices, and some Virtex-4 FX ES devices.
In the later Virtex-4 stepping levels, an update has been made to the silicon that TCONFIG and DCM_RESET are no longer required and no longer specified. This update enables a smaller clock stop macro implementation.
In ISE design tool versions 7.1.03i and later, MAP automatically instantiates a clock stop macro for each DCM in a design for the Virtex-4 LX/SX Production Step 2 and higher devices, and Virtex-4 FX ES4 and Production devices. The macro adds approximately 15 slices per DCM. The function of this macro is to detect a clock stop on the two clock input pins of the DCM (CLKIN and CLKFB). When a clock stop is detected, the macro internally asserts and holds the RST signal of the DCM, which triggers the internal oscillator of the DCM to toggle the delay lines.
When the input clock returns, the user must manually assert the DCM reset for at least 200 ms to resume proper DCM functionality.
To specify to MAP the stepping level of the silicon targeted, put the following line in your UCF file:
Where "#" is the stepping level of the device.
For more information about Virtex-4 steppings, see (Xilinx Answer 21605)
Note: For FX devices, since the ISE default stepping level is 0, the auto calibration macro will be inserted automatically if the stepping level is not set by the user. Ensure that the CONFIG STEPPING constraint is set properly according to the device you are targeting.
Disabling Macro Insertion
If you can ensure that the clock source for any particular DCM will never stop, the extra logic insertion can be disabled using one of the following two methods:
- If none of the DCMs in your design require the clock stop circuitry (i.e., the DCM source clocks will never stop), you can globally disable the logic insertion by setting the XIL_DCM_AUTOCALIBRATION_OFF environment variable.
- You can also disable insertion on an individual basis by applying the DCM_AUTOCALIBRATION attribute to specific DCMs. Acceptable values are TRUE and FALSE, where TRUE (the default value) allows MAP to insert the clock stop circuitry, and FALSE disables the logic insertion. You can add this attribute to the HDL design source using the VHDL generic or Verilog defparam, or it can be entered as a synthesis attribute (check with your synthesis tool for the appropriate syntax).
When applying this attribute in the UCF file, the syntax is as follows:
For each DCM that requires extra logic insertion, a warning message similar to the following will occur:
Note: You can safely ignore these messages.
If I have already instantiated the DCM_STANDBY macro in (Xilinx Answer 21127), will ISE 7.1i Service Pack 3 (7.1.03i) software insert extra logic for DCMs?
The DCM_STANDBY macro has the 'DCM_AUTOCALIBRATION = FALSE' attribute set, which prevents the software from adding more logic.
The DCM_STANDBY macro is the work-around for Virtex-4 LX/SX ES and Step 1 and Virtex-4 FX ES devices. Will it work with later stepping silicon?
Yes, the DCM_STANDBY will work with later stepping silicon. However, the DCM_STANDBY macro is much larger (100 slices vs. 15 slices).
Consequently, if you are only targeting later stepping silicon, it is more efficient to let the software insert the macro instead of using the DCM_STANDBY macro.
If I have both LX Step 1 and Step 2 devices and want to use only one bitstream, what should I do?
Because stepping devices are completely backwards compatible, you should design for the smaller step number. In this case, instantiate the DCM_STANDBY macro, and set CONFIG STEPPING="1"; in the UCF file.