| AR# |
21436 |
| Part |
FPGA-RocketIO |
| Last Modified |
2005-07-14 00:00:00.0 |
| Status |
Active |
| Keywords |
MGT, RocketIO, RocketI/O, Virtex-4, Architecture Wizard, Architecure Wizard, RXCLKMODE, RXASYNCDIV, TXCLKMODE,TXASYNCDIV |
Description
Keywords: MGT, RocketIO, RocketI/O, Virtex-4, Architecture Wizard, Architecure Wizard, RXCLKMODE, RXASYNCDIV, TXCLKMODE,TXASYNCDIV
Urgency: Standard
General Description:
Some attributes in the RocketIO Wizard such as RXCLKMODE, RXASYNCDIV, TXCLKMODE, and TXASYNCDIV are different from those in the Clocking Decision Flow shown in the User Guide.
Solution
There are multiple combinations that build one divide ratio. Although the values are different, the final divider ratio will be same. For example, in the picture, there are two combinations that achieve divide by 20. The red line passes the top dividers /4 and /5, which are the synchronous dividers. Also, the blue line passes the bottom dividers /4 and /5, which are the asynchronous dividers.
Dividers in receiver For details about the Receive Clocking Decision Flow or the Transmit Clock Decision Flow, please see the RocketIO User Guide:
http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?category=User+Guides
