When I run a process on a schematic design module, the following error occurs:
"Started process "View HDL Functional Model".
ERROR:DesignEntry:222 - Error: Net 'net-name' cannot be connected both to an input port and an instance output pin."
In 6.xi, the message was:
"ERROR:DesignEntry:77 - Error: Net 'net-name' is connected to input ports and instance output pins. A net cannot be connected to both input ports and instance output pins."
Before a schematic design is implemented, it is first converted to either Verilog or VHDL (depending on the setting of the Generated Simulation Language property). As part of the conversion process, a Design Rule Check (DRC) will be run on the selected schematic and any underlying schematics. "Error: DesignEntry:222" indicates that an I/O Marker with an Input Port polarity is connected to an output pin of one of the symbol instances in the schematic drawing. This is not allowed, as it would create an electrical source conflict.
If an Input or Output port has been removed from the net in question, verify that the port PortPolarity is changed to "Not a Port." To do this, right-click the net and select Object Properties (or double-click the net). If the internal net has a PortPolarity value of Input, Output, or Bidirectional, select PortPolarity, then use "Edit Attribute" to change the setting to "Not a Port."
Another way to remove the designation is to add an input marker to the net and then select "Remove the Marker" in the Add I/O Marker Options window and click the net in question.